Voltage level responsive circuit

Claim 2

A voltage level responsive circuit comprising first (T1, T2) and second inverter (T5, T6) circuits, each coupled between a voltage source (Vdd) and a common voltage node (N1), each inverter including an input responsive device (T2 or T6) and a first impedance means (T1 or T5), the input of the first inverter being responsive to an input signal (V IN) and the output of the first inverter (T1, T2) being coupled to the input of the second inverter (T5, T6), a first switching means (T3) having a control electrode and two current conducting electrodes, the current conducting electrodes being coupled between the common voltage node (N1) and a reference voltage node (N2), and means coupling the output of the second inverter (T5, T6) to the control electrode of the first switching means (T3), and a second switching means (T7) coupled between the reference voltage node (N2) and a source of reference voltage, the second switching means (T7) being responsive to a circuit enabling signal (SET) to selectively apply power to the voltage level responsive circuit, after the level of the input signal has been altered.

Claim 3

The level responsive circuit of Claim 1 further including second impedance means (T4) for causing positive feedback between the output of the first inverter (T1, T2) and the common voltage node (N1).

Claim 4

The level responsive circuit of Claim 2 wherein the second impedance means (T4) comprises a three-terminal semiconductor device having a pair of current conducting electrodes and a contro) electrode.

Claim 5

The level responsive circuit of Claim 3 wherein the three-terminal semiconductor device (T4) has its current conducting electrodes coupled between the voltage source (Vdd) and the common voltage node (N1) and its control electrode coupled to the output of the first inverter (T1, T2).

Claim 6

The level responsive circuit of Claim 1 wherein each of the input responsive devices (T2, T6), first impedance means (T1, T5) and switching means (T3, T7) are IGFET devices.

Claim 7

A level sensitive data signal sensing circuit for an integrated memory circuit including an array of addressable memory devices (1, 1; 1, 2; 2, 1; 2, 2; Fig. 2), at least one of which when addressed will cause the voltage on a precharged data sense line (DBT or DBB) to be changed, the data signal sensing circuit (SAT or SAB) having an input coupled to the data sense line (DBT or DBB) and being enabled by an amplifier set signal (SET) after the selection of an addressed memory device, the signal sensing circuit (SAT, SAB) comprising a first data signal responsive inverter circuit (T1, T2; Fig. 1) coupled between a first source of supply voltage (Vdd) and a common voltage node (N1), the output of the first inverter corresponding to the sensed data signal, a second inverter circuit (T5, T6) coupled between the first source of supply voltage (Vdd) and the common voltage node (N1), the input of the second inverter circuit (T5, T6) being coupled to the output of the first inverter circuit (T1, T2), and a series circuit (T3, T7) coupling the common voltage node (N1) to a second source of supply voltage (GROUND), the series circuit including an amplifier set signal-responsive switching device (T7) and a voltage responsive current conducting device (T3) having a control electrode coupled to the output of the second inverter circuit (T5, T6), said amplifier set signal being operable after the level of the data signal has been altered.

Claim 8

A level sensitive data signal sensing circuit for an integrated memory circuit including an array of addressable memory devices (1, 1; 1, 2; 2, 1; 2, 2; Fig. 2), at least one of which when addressed will cause the voltage on a precharged data sense line (DBT or DBB) to be changed, the data signal sensing circuit (SAT or SAB) having an input coupled to the data sense line (DBT or DBB) and being enabled by an amplifier set signal (SET) after the selection of an addressed memory device, the signal sensing circuit (SAT, SAB) comprising a first data signal responsive inverter circuit (T1, T2; Fig. 1) coupled between a first source of supply voltage (Vdd) and a common voltage node (N1), the output of the first inverter corresponding to the sensed data signal, a second inverter circuit (T5, T6) coupled between the first source of supply voltage (Vdd) and the common voltage node (N1), the input of the second inverter circuit (T5, T6) being coupled to the output of the first inverter circuit (T1, T2), and a series circuit (T3, T7) coupling the common voltage node (N1) to a second source of supply voltage (GROUND), the series circuit including an amplifier set signal-responsive switching device (T7) and a voltage responsive current conducting device (T3) having a control electrode coupled to the output of the second inverter circuit (T5, T6), said amplifier set signal being operable after the level of the data signal has been altered.

Claim 9

The data signal sensing circuit of Claim 6 wherein the first and second inverter circuits (T1, T2; T5, T6), the switching device (T7) and the current conducting device (T3) all comprise IGFET devices.

Claim 10

The data signal sensing circuit of Claims 6 and 7 further including an IGFET device (T4) having a gate electrode and two current conducting electrodes, the gate electrode coupled to the output of the first inverter (T1, T2) and the current conducting electrodes coupled between the first source of supply voltage (Vdd) and the common voltage node (N1).