Single-ended sense amplifier with positive feedback

Claim 2

A sense amplifier for indicating the state of a bitline of an integrated-circuit logic array comprising: a supply voltage source, an activating transistor pair connected to an activating signal source, a sensing transistor pair connected to said activating transistor pair and to said bitline, an output driver transistor pair connected to said sensing transistor pair, a feedback transistor connecting the output of said output driver transistor pair to the input of said output driver transistor pair, and an inverter transistor pair connecting said output driver transistor pair to an output terminal of said sense amplifier.

Claim 3

The sense amplifier of claim 1 in which the source/drain paths of said activating transistor pair are connected in series between said voltage source and a reference potential, in which the gate of the transistor of said activating pair nearest said voltage source is connected to said activating signal source, and in which the gate of the other transistor of said activating pair is connected to said voltage source.

Claim 4

The sense amplifier of claim 2 in which said activating transistor pair is comprised of N-channel field-effect transistors.

Claim 5

The sense amplifier of claim 2 in which the source/drain paths of said sensing transistor pair are connected in series between said voltage source and said bitline, in which the gate of the transistor of said sensing pair nearest said voltage source is connected to a reference potential, and in which the gate of the other transistor of said sensing pair is connected to the common terminal of said series-connected activating transistor pair.

Claim 6

The sense amplifier of claim 4 in which said sensing transistor pair is comprised of a P-channel transistor nearest said voltage source and of a N-channel transistor nearest said bitline.

Claim 7

The sense amplifier of claim 4 in which the source/drain paths of said output driver transistor pair are connected in series between said voltage source and a reference potential, in which the gate of the transistor of said output pair nearest said voltage source is connected to the common terminal of said series-connected sensing amplifier pair, and in which the gate of the other transistor of said output pair is connected to said voltage source.

Claim 8

The sense amplifier of claim 6 in which said output driver transistor pair is comprised of a P-channel transistor nearest said voltage source and of a N-channel transistor nearest said reference potential.

Claim 9

The sense amplifier of claim 6 in which the source/drain path of said feedback transistor is connected between the gate of the transistor of said output pair nearest said voltage source and reference potential and in which the gate of said feedback transistor is connected to the common terminal of said output driver transistor pair.

Claim 10

The sense amplifier of claim 8 in which said feedback transistor is a N-channel transistor.

Claim 11

The sense amplifier of claim 8 in which the source/drain paths of said inverter transistor pair ar connected in series between said voltage source and reference potential, in which the gates of each of said inverter pair are connected to the common terminal of said output driver transistor pair, and in which the common terminal of said inverter pair is connected to said output terminal of said sense amplifier.

Claim 12

The sense amplifier of claim 10 in which the transistor of said inverter pair nearest said voltage source is a P-channel transistor and in which the other transistor of said inverter pair is a N-channel transistor.

Claim 13

An amplifier for sensing the state of an integrated-circuit logic-array bitline comprising: a series sensing transistor pair of opposite channel type connected at one end to said bitline and at the other end to a voltage source and with gate of the P-channel transistor of said sensing pair nearest said source connected to reference potential and with gate of the N-channel transistor of said sensing pair connected to an activating transistor pair, a series output driver transistor pair of opposite channel type connected at one end to said voltage source and at the other end to said reference potential and with gate of the P-channel transistor of said driver pair nearest said source connected to the common terminal of said sensing transistor pair and with gate of the N-channel transistor of said driver pair connected to said voltage source, and an N-channel feedback transistor connected between the common terminal of said sensing pair and said reference potential and with a gate connected to the common terminal of said driver pair, wherein the electrical signal at the common terminal of said driver pair is inverted by an inverter transistor pair to form the output of said amplifier.

Claim 14

An amplifier for sensing the state of an integrated-circuit logic-array bitline comprising: a series sensing transistor pair of opposite channel type connected at one end to said bitline and at the other end to a voltage source and with gate of the P-channel transistor of said sensing pair nearest said source connected to reference potential and with gate of the N-channel transistor of said sensing pair connected to an activating transistor pair, a series output driver transistor pair of opposite channel type connected at one end to said voltage source and at the other end to said reference potential and with gate of the P-channel transistor of said driver pair nearest said source connected to the common terminal of said sensing transistor pair and with gate of the N-channel transistor of said driver pair connected to said voltage source, and an N-channel feedback transistor connected between the common terminal of said sensing pair and said reference potential and with a gate connected to the common terminal of said driver pair, wherein the electrical signal at the common terminal of said driver pair is inverted by an inverter transistor pair to form the output of said amplifier.