US4758749A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS current sense amplifier
Assignee: National Semiconductor Corp
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Filing: 1987-05-19
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Granted: 1988-07-19
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Expires: 2007-05-19
Abstract
Abstract A CMOS current sense amplifier is composed of an output inverter gate, a combined driver and biasing stage that biases the output inverter gate and drives its transistors, and an input stage that acts to reduce the input voltage swing. The circuit responds rapidly to input current changes and is therefore useful in sensing the currents in large memory arrays that have large shunt capacitance values.
Inventors
- 👤 A. Karl Rapp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:32
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16533; G01R19/16557; G01R19/145; G01R19/15; G01R31/00; G01R31/28; G01R31/30; G01R31/3004; G11; G11C; G11C29/00; G11C29/04; G11C29/50; H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/345; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
182 words
A CMOS current sensing amplifier having an input terminal coupled to a memory element to determine the electrical state thereof and an output terminal which produces a voltage state indicative of the state of the current in said memory element, said amplifier comprising; an output inverter gate including a P channel transistor inverter and an N channel transistor inverter, said output inverter gate having an output terminal that acts as said amplifier output terminal and P channel and N channel transistor gate input terminals; voltage dropping means coupled between said P channel transistor gate and said N channel transistor gate to provide bias for said output inverter gate; a P channel transistor inverter having an output coupled to said P channel transistor gate and an input coupled to said amplifier input terminal; an N channel transistor inverter having an output coupled to said N channel transistor gate and an input coupled to said amplifier input terminal; and an N channel transistor source follower having an input coupled to said P channel transistor gate and an output coupled to said amplifier input terminal.
Claim 2
Dependent Claim
182 words
A CMOS current sensing amplifier having an input terminal coupled to a memory element to determine the electrical state thereof and an output terminal which produces a voltage state indicative of the state of the current in said memory element, said amplifier comprising; an output inverter gate including a P channel transistor inverter and an N channel transistor inverter, said output inverter gate having an output terminal that acts as said amplifier output terminal and P channel and N channel transistor gate input terminals; voltage dropping means coupled between said P channel transistor gate and said N channel transistor gate to provide bias for said output inverter gate; a P channel transistor inverter having an output coupled to said P channel transistor gate and an input coupled to said amplifier input terminal; an N channel transistor inverter having an output coupled to said N channel transistor gate and an input coupled to said amplifier input terminal; and an N channel transistor source follower having an input coupled to said P channel transistor gate and an output coupled to said amplifier input terminal.
Claim 3
Dependent Claim
26 words
The current sensing amplifier of claim 1 wherein said N channel transistor source follower has the smallest transistor channel width to length ratio in said amplifier.
Claim 4
Dependent Claim
25 words
The current sensing amplifier of claim 1 wherein said N channel transistor inverter has the largest transistor channel width to length ratio in said circuit.
Claim 5
Dependent Claim
24 words
The current sensing amplifier of claim 1 wherein said voltage dropping means comprise an N channel transistor having its drain connected to its gate.
Claim 6
Dependent Claim
47 words
The current sensing amplifier of claim 2 wherein said transistors are selected so that the current flowing in said N channel voltage transistor under logic zero input conditions is approximately equal to the current flowing in said N channel transistor source follower under logic one input conditions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-19 | 1992-01-18 | 1992-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-19 | 1996-01-18 | 1996-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-19 | 2000-01-18 | 2000-07-19 | $7700.00 | Window Closed / Lapsed |