Threshold amplifier for IC fabrication using CMOS technology

Claim 2

A threshold amplifier comprising: a. a first and a second terminal for connection to a bias supply, b. a first series circuit connected between said first and second supply terminals comprising: i. first FET device having the source connected to said first supply terminal, ii. a diode connected second FET device having the drain and gate connected together, the interconnection being conductively connected to the drain of said first device, iii. a current sensing resistance connected between the source of said second device and said second supply terminal, and iv. means to establish a desired current in said first series circuit; and c. a second series circuit connected between said first and second supply terminals comprising: i. a third, FET device having the source connected to said first supply terminal, and the gate of said third FET device is conductively connected to the gate of said first FET device, and ii. a fourth FET device having the drain thereof connected to the drain of said third device, the source of said fourth device being connected to said second supply terminal, said first and third devices being of the same polarity type, and second and fourth devices being of the same polarity type, and complementary to said first and third devices, d. said first and third devices having fixed conductivity ratio in each series path, e. means connecting the gate of said fourth device to the gate-drain connection of said second device to equalize the gate to source voltage of said fourth device to the voltage between the gate of said second device and said second supply terminal, f. an input terminal for coupling a current to be sensed into said current sensing resistance, the voltage drop attributable thereto displacing the voltage of the source of said second device in relation to the voltage at said second supply terminal, and in turn the gate to source voltage of said fourth device, said fourth device being in a low conduction state in the absence of sensed current and in a high conduction state when said sensed current exceeds a given value, said third device being capable of conduction throughout, and g. output means coupled to the drain connection of said third and fourth devices to provide a first digital output level when the sensed current is below said given value and a second digital output level, when the sensed current is above said given value.

Claim 3

The threshold amplifier as set forth in claim 1 wherein: a. said first and second supply terminals are respectively the positive terminal and negative terminal of said supply; and b. said first and third FET devices are p-channel devices, and said second and fourth FET devices are n-channel devices.

Claim 4

The threshold amplifier as set forth in claim 1 wherein: a. said first and second supply terminals are respectively the negative terminal and positive terminal of said supply; and b. said first and third FET devices are n-channel devices, and said second and fourth FET devices are p-channel devices.

Claim 5

The threshold amplifier as set forth in claim 1 wherein: a. said first FET device is diode connected, having the gate and drain connected together, b. said means to establish a current in said first series circuit is a fifth FET device, conductively connecting the gate-drain of said first device to the gate-drain of said second device, said fifth device being of low conductivity relative to said first and second devices, and c. the gates of said first and third devices being connected together to equalize the gate to source voltages and set said conductivity ratio.

Claim 6

The threshold amplifier as set forth in claim 4 wherein: the width of the gate region of said second device differs from that of said fourth device to adjust the diode voltage drop therein in relation to the diode voltage drop of said first device, and in turn to displace the value of sensed current at which said third device beings to conduct.

Claim 7

The threshold amplifier as set forth in claim 5 wherein: a. said first and second supply terminals are respectively the positive terminal and negative terminals of said supply; and b. said first and third FET devices are p-channel devices, and said second and fourth FET devices are n-channel devices, c. the substrates of said first and third devices are connected to said positive terminal, and the substrates of said second and fourth devices are connected to said negative terminal.

Claim 8

The threshold amplifier as set forth in claim 6 wherein: said output means includes an inverting C-MOS buffer amplifier.

Claim 9

The threshold amplifier as set forth in claim 6 wherein: said output means includes an inverting buffer amplifier with hysteresis.

Claim 10

The threshold amplifier as set forth in claim 4 wherein: said fifth FET device is diode connected, having the gate thereof connected to the drain thereof.

Claim 11

A threshold amplifier as set forth in claim 1 wherein: said first FET device is of low conductivity providing said means for establishing a desired current in said first series circuit and wherein said third FET device is of low conductivity, the geometries of said first and third FETs providing said fixed conductivity ratio.

Claim 12

A threshold amplifier as set forth in claim 10 wherein said first and third devices have their gates connected together to equalize the gate to source voltages and set said conductivity ratio.

Claim 13

A threshold amplifier comprising: a. a first and second terminal for connection to a bias supply, and b. a first series circuit connected between said first and second supply terminals comprising: i. first FET device having the source connected to said first supply terminal, and having the drain and gate connected together, said first FET device providing means for establishing a desired current in said first series circuit, ii. a diode-connected second FET device having the drain and gate connected together, the interconnection being conductively connected to the drain of said first device, iii. a current sensing resistance connected between the source of said second device and said second supply terminal, and c. a second series circuit connected between said first and second supply terminals comprising: i. a third FET device having the source connected to said first supply terminal, and having the drain and gate connected together, and ii. a fourth FET device having the drain thereof connected to the drain of said third device, the source of said fourth device being connected to said second supply terminal, said first and third devices being of the same polarity type, and second and fourth devices being of the same polarity type, and complementary to said first and third devices, d. said first and third devices having fixed conductivity ratio in each series path, e. means connecting the gate of said fourth device to the gate-drain connection of said second device to equalize the gate to source voltage of said fourth device to the voltage between the gate of said second device and said second supply terminal, f. an input terminal for coupling a current to be sensed into said current sensing resistance, the voltage drop attributable thereto displacing the voltage of the source of said second device in relation to the voltage at said second supply terminal, and in turn the the gate to source voltage of said fourth device, said fourth device being in a low conduction state in the absence of sensed current and in a high conduction state when said sensed current exceeds a given value, said third device being capable of conduction throughout, and g. output means coupled to the drain connection of said third and fourth devices to provide a first digital output level when the sensed current is below said given value and a second digital output level, when the sensed current is above said given value.

Claim 14

A threshold amplifier comprising: a. a first and second terminal for connection to a bias supply, and b. a first series circuit connected between said first and second supply terminals comprising: i. first FET device having the source connected to said first supply terminal, and having the drain and gate connected together, said first FET device providing means for establishing a desired current in said first series circuit, ii. a diode-connected second FET device having the drain and gate connected together, the interconnection being conductively connected to the drain of said first device, iii. a current sensing resistance connected between the source of said second device and said second supply terminal, and c. a second series circuit connected between said first and second supply terminals comprising: i. a third FET device having the source connected to said first supply terminal, and having the drain and gate connected together, and ii. a fourth FET device having the drain thereof connected to the drain of said third device, the source of said fourth device being connected to said second supply terminal, said first and third devices being of the same polarity type, and second and fourth devices being of the same polarity type, and complementary to said first and third devices, d. said first and third devices having fixed conductivity ratio in each series path, e. means connecting the gate of said fourth device to the gate-drain connection of said second device to equalize the gate to source voltage of said fourth device to the voltage between the gate of said second device and said second supply terminal, f. an input terminal for coupling a current to be sensed into said current sensing resistance, the voltage drop attributable thereto displacing the voltage of the source of said second device in relation to the voltage at said second supply terminal, and in turn the the gate to source voltage of said fourth device, said fourth device being in a low conduction state in the absence of sensed current and in a high conduction state when said sensed current exceeds a given value, said third device being capable of conduction throughout, and g. output means coupled to the drain connection of said third and fourth devices to provide a first digital output level when the sensed current is below said given value and a second digital output level, when the sensed current is above said given value.

Claim 15

The threshold amplifier as set forth in claim 12 a. said first and second supply terminals are respectively the positive terminal and negative terminal of said supply; and b. said first and third FET devices are P-channel devices, and said second and fourth FET devices are N-channel devices.

Claim 16

The threshold amplifier as set forth in claim 12 wherein: a said first and second supply terminals are respectively the negative terminal and positive terminal of said supply; and b. said first and third FET devices are n-channel devices and said second and fourth FET devices are p-channel devices.