Vertical field effect transistor with improved control of low resistivity region geometry

Claim 1

A method of making a vertical field effect transistor comprising the steps of: providing a semiconductor substate; forming a epitaxial region of a first conductivity type on the substrate; forming a gate oxide on a surface of the epitaxial region; forming a patterned polysilicon gate on the gate oxide; forming a base region of a second conductivity type in the substrate using the patterned polysilicon gate as a mask; forming a source region of the first conductivity type in the base region using the patterned polysilicon gate as a mask; forming an oxide spacer on a sidewall of the patterned polysilicon gate using hotwall TEOS process, wherein the spacer is 0.3-0.8 microns thick; forming a low resistivity region of the second conductivity type underneath the source using the sidewall spacer as a mask, wherein the low resistivity region is completely covered by the source; forming an oxide layer completely covering the source; selectively patterning the oxide layer to expose a first portion of the source; removing the first portion of the source to expose a portion of the low resistivity region; isotropically etching the oxide layer to expose a second portion of the source; and forming a source electrode in contact with the low resistivity region and the source.

Claim 2

A method of making a vertical field effect transistor comprising the steps of: providing a semiconductor substate; forming a epitaxial region of a first conductivity type on the substrate; forming a gate oxide on a surface of the epitaxial region; forming a patterned polysilicon gate on the gate oxide; forming a base region of a second conductivity type in the substrate using the patterned polysilicon gate as a mask; forming a source region of the first conductivity type in the base region using the patterned polysilicon gate as a mask; forming an oxide spacer on a sidewall of the patterned polysilicon gate using hotwall TEOS process, wherein the spacer is 0.3-0.8 microns thick; forming a low resistivity region of the second conductivity type underneath the source using the sidewall spacer as a mask, wherein the low resistivity region is completely covered by the source; forming an oxide layer completely covering the source; selectively patterning the oxide layer to expose a first portion of the source; removing the first portion of the source to expose a portion of the low resistivity region; isotropically etching the oxide layer to expose a second portion of the source; and forming a source electrode in contact with the low resistivity region and the source.