Patent US5153846A successfully refreshed from Google Patents.
US5153846A
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Digital shift register using random access memory
Assignee: Nokia Bell Labs
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Filing: 1990-07-30
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Granted: 1992-10-06
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Expires: 2010-07-30
Abstract
Abstract A tapped digital shift register suitable for use with a finite-impulse-response (FIR) filter in applications such as high-definition television is implemented using a random-access memory (RAM). The RAM contains x words having yz bits each, where x represents the number of elements in each section of the shift register, y represents the number of taps and z represents the number of bits in each element. Words are continuously read from and written back into the RAM. Before being written back, each word is modified by removing a z-bit portion from one end and appending a z-bit portion representing new information to the other end. The shift-register architecture disclosed is particularly suited for implementation on very-large-scale integrated circuits together with the FIR filter circuits.
Inventors
- 👤 Sailesh K. Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:24
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785; G06F5/00; G06F5/06; G06F5/16; H; H03; H03H; H03H17/00; H03H17/02; H03H17/06
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
86 words
A shift register for digital words, which comprises: a random access memory, means for cycling through the addresses in said memory, means for reading each addressed word from said memory, means for modifying each memory word read by removing a portion from one end of said word and appending a portion to the other end of said word, said appended portion being the next digital word to be entered into said shift register, and mean for writing the output from said modifying means into said memory.
Claim 2
Dependent Claim
86 words
A shift register for digital words, which comprises: a random access memory, means for cycling through the addresses in said memory, means for reading each addressed word from said memory, means for modifying each memory word read by removing a portion from one end of said word and appending a portion to the other end of said word, said appended portion being the next digital word to be entered into said shift register, and mean for writing the output from said modifying means into said memory.
Claim 3
Dependent Claim
34 words
The shift register of claim 1 in which said means for modifying further comprises: means for applying at least one intermediate portion of the output from said modifying means to a corresponding output tap.
Claim 4
Dependent Claim
41 words
The shift register of claim 1 in which said memory is configured in more than one section and said means for addressing, means for reading and means for writing further comprise means for reading from and writing into said sections sequentially.
Claim 5
Dependent Claim
39 words
The shift register of claim 3 in which said memory is configured in two sections and said means for addressing, means for reading and means for writing further comprise means for reading from and writing into said sections alternately.
Claim 6
Dependent Claim
16 words
The shift register of claim 1 in which said memory is a static random access memory.
Claim 7
Dependent Claim
16 words
The shift register of claim 1 in which said memory is a dynamic random access memory.
Claim 8
Dependent Claim
116 words
A shift register for use with a multi-tap finite-impulse-response filter acting on an input stream of digital words, which comprises: a random access memory, means for cycling through the addresses in said memory, means for reading each addressed word from said memory, means for modifying each memory word read by removing a portion from one end of said word and appending a portion to the other end of said word, said appended portion being the next digital word to be entered into said filter, means for writing the output word from said modifying means into said memory, and means for applying portions of the output word from said modifying means to the taps of said filter.
Claim 9
Dependent Claim
116 words
A shift register for use with a multi-tap finite-impulse-response filter acting on an input stream of digital words, which comprises: a random access memory, means for cycling through the addresses in said memory, means for reading each addressed word from said memory, means for modifying each memory word read by removing a portion from one end of said word and appending a portion to the other end of said word, said appended portion being the next digital word to be entered into said filter, means for writing the output word from said modifying means into said memory, and means for applying portions of the output word from said modifying means to the taps of said filter.
Claim 10
Dependent Claim
41 words
The shift register of claim 7 in which said memory is configured in more than one section and said means for addressing, means for reading and means for writing further comprise means for reading from and writing into said sections sequentially.
Claim 11
Dependent Claim
39 words
The shift register of claim 8 in which said memory is configured in two sections and said means for addressing, means for reading and means for writing further comprise means for reading from and writing into said sections alternately.
Claim 12
Dependent Claim
16 words
The shift register of claim 7 in which said memory is a static random access memory.
Claim 13
Dependent Claim
16 words
The shift register of claim 7 in which said memory is a dynamic random access memory.
Claim 14
Dependent Claim
190 words
A shift register for use with a finite-impulse-response filter having y taps and an input stream of z-bit digital words representing a horizontally-scanned video signal, each digital word representing a picture element in the picture represented by aid video signal, each horizontal scan line in said picture having x picture elements, said filter being configured to generate signals representing a set of y picture elements aligned vertically in said picture, which comprises: a random access memory having x addressable words and wherein the number of bits in each word is y X z, means for cycling through the addresses in said memory means for reading each addressed word from said memory, means for modifying each memory word read by removing a z-bit portion form one end of said word and appending a z-bit portion to the other end of said word, said appended portion being the next digital word to be entered into said filter, means for writing the output word from said modifying means into said memory, and means for applying y z-bit portions of the output word from said modifying means to the y taps of said filter.
Claim 15
Dependent Claim
190 words
A shift register for use with a finite-impulse-response filter having y taps and an input stream of z-bit digital words representing a horizontally-scanned video signal, each digital word representing a picture element in the picture represented by aid video signal, each horizontal scan line in said picture having x picture elements, said filter being configured to generate signals representing a set of y picture elements aligned vertically in said picture, which comprises: a random access memory having x addressable words and wherein the number of bits in each word is y X z, means for cycling through the addresses in said memory means for reading each addressed word from said memory, means for modifying each memory word read by removing a z-bit portion form one end of said word and appending a z-bit portion to the other end of said word, said appended portion being the next digital word to be entered into said filter, means for writing the output word from said modifying means into said memory, and means for applying y z-bit portions of the output word from said modifying means to the y taps of said filter.
Claim 16
Dependent Claim
41 words
The shift register of claim 12 in which said memory is configured in more than one section and said means for addressing, means for reading and means for writing further comprise means for reading from and writing into said sections sequentially.
Claim 17
Dependent Claim
39 words
The shift register of claim 13 in which said memory is configured in two sections and said means for addressing, means for reading and means for writing further comprise means for reading from and writing into said sections alternately.
Claim 18
Dependent Claim
16 words
The shift register of claim 12 in which said memory is a static random access memory.
Claim 19
Dependent Claim
16 words
The shift register of claim 12 in which said memory is a dynamic random access memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-06 | 1996-04-06 | 1996-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-06 | 2000-04-06 | 2000-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-06 | 2004-04-06 | 2004-10-06 | $7700.00 | Window Closed / Lapsed |