US4777612A
Expired / Lapsed
US
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Digital signal processing apparatus having a digital filter
Assignee: NEC Corp
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Filing: 1984-10-05
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Granted: 1988-10-11
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Expires: 2004-10-05
Abstract
Abstract A digital signal processing apparatus with a rate-conversion function has at least two digital filters and a memory. A digital signal stored in the memory is selectively transferred to the at least two digital filters. These digital filters perform a filtering operation in parallel, and the results from each of the digital filters are alternately derived by a multiplexer. Thus, high-speed filtering can be executed. The memory temporarily stores a time-division-multiplexed signal which is sequentially read out of the memory and selectively transferred to the digital filters. Thus, a plurality of digital signals can be filtered by the same digital filters without an increase in hardware elements. Therefore, the digital filter section can be integrated in a single semiconductor chip. A shift register may be used as the memory, whereby a circuit arrangement of the digital filter section can be extremely simplified.
Inventors
- 👤 Yasuharu Tomimitsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:23
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0607; H03H17/0248; H03H17/0264; H03H17/0273; H03H17/0275; H03H17/0276; H03H17/0283; H03H17/0292; H03H17/0621; H03H17/0635; H03H17/065; H03H17/0657; H03H2218/00; H03H2218/06
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
294 words
A digital signal processing apparatus processing a first digital signal of a first channel and a second digital signal of a second channel which are applied thereto in a time-division manner comprising: an even-order digital filter; an odd-order digital filer; first means for receiving the first digital signal at a first timing; second means for receiving the second digital signal at a second timing subsequent to said first timing; third means coupled to said even-order digital filter and said first means for entering the first digital signal into said even-order digital signal at the second timing, said even-order digital filter performing a first filter operation on said first digital signal at the second timing; fourth means coupled to said even-order digital filter and said second means for entering the second digital signal into said even-order digital filter at a third timing subsequent to said second timing, said even-order digital filter performing a second filter operation on said second digital signal at the third timing; fifth means coupled to said odd-order digital filter and said first means for entering the first digital signal into said odd-order digital filter at said third timing, said odd-order digital filter performing a third filter operation on said first digital signal at the third timing; and output means coupled to said even-order digital filter and said odd-order digital filter for outputting a result of the first filter operation from said even-order digital filter at the third timing, outputting a result of the third filter operation from said odd-order digital filter in a first period of a fourth timing subsequent to said third timing, and outputting a result of the second filter operation from said even-order digital filter in a second period subsequent to said first period of said fourth timing.
Claim 2
Dependent Claim
294 words
A digital signal processing apparatus processing a first digital signal of a first channel and a second digital signal of a second channel which are applied thereto in a time-division manner comprising: an even-order digital filter; an odd-order digital filer; first means for receiving the first digital signal at a first timing; second means for receiving the second digital signal at a second timing subsequent to said first timing; third means coupled to said even-order digital filter and said first means for entering the first digital signal into said even-order digital signal at the second timing, said even-order digital filter performing a first filter operation on said first digital signal at the second timing; fourth means coupled to said even-order digital filter and said second means for entering the second digital signal into said even-order digital filter at a third timing subsequent to said second timing, said even-order digital filter performing a second filter operation on said second digital signal at the third timing; fifth means coupled to said odd-order digital filter and said first means for entering the first digital signal into said odd-order digital filter at said third timing, said odd-order digital filter performing a third filter operation on said first digital signal at the third timing; and output means coupled to said even-order digital filter and said odd-order digital filter for outputting a result of the first filter operation from said even-order digital filter at the third timing, outputting a result of the third filter operation from said odd-order digital filter in a first period of a fourth timing subsequent to said third timing, and outputting a result of the second filter operation from said even-order digital filter in a second period subsequent to said first period of said fourth timing.
Claim 3
Dependent Claim
32 words
An apparatus as claimed in claim 1, wherein said first means includes a first memory working as a delay circuit, said second means including a second memory working as a delay circuit.
Claim 4
Dependent Claim
48 words
An apparatus as claimed in claim 1, wherein said first means and said second means consist of a single shift register having a plurality of shift stages, even-order shift stages being coupled to said even-order digital filter, and odd-order shift stages being coupled to said odd-order digital filter.
Claim 5
Dependent Claim
32 words
An apparatus as claimed in claim 3, wherein each of said even-order digital filter and said odd-order digital filter includes a memory for storing multiplied data and a shifting and adding circuit.
Claim 6
Dependent Claim
42 words
An apparatus as claimed in claim 1, wherein said output means includes a multiplexer which sequentially outputs first the result of the first filter operation, then the result of the third filter operation and lastly the result of the second filter operation.
Claim 7
Dependent Claim
142 words
A digital signal processing apparatus having a two-fold rate conversion function for two channels comprising a shift register receiving a first digital signal from a first channel and a second digital signal from a second channel in a time-division manner and having a plurality of shift stages which alternately shifts the received first digital signal and the second digital signal, an even-order digital filter coupled to even-order shift stages and performing a filter operation on outputs of the even-order shift stages, an odd-order digital filter coupled to odd-order shift stages and performing a filter operation on outputs of the odd-order shift stages, and a multiplexer coupled to said even-order digital filter and said odd-order digital filter and alternately outputting a result of the filter operation of said even-order digital filter and a result of the filter operation of said odd-order digital filter.
Claim 8
Dependent Claim
142 words
A digital signal processing apparatus having a two-fold rate conversion function for two channels comprising a shift register receiving a first digital signal from a first channel and a second digital signal from a second channel in a time-division manner and having a plurality of shift stages which alternately shifts the received first digital signal and the second digital signal, an even-order digital filter coupled to even-order shift stages and performing a filter operation on outputs of the even-order shift stages, an odd-order digital filter coupled to odd-order shift stages and performing a filter operation on outputs of the odd-order shift stages, and a multiplexer coupled to said even-order digital filter and said odd-order digital filter and alternately outputting a result of the filter operation of said even-order digital filter and a result of the filter operation of said odd-order digital filter.
Claim 9
Dependent Claim
27 words
An apparatus as claimed in claim 6, wherein said even-order digital filter and said odd-order digital filter are positioned rightwardly and leftwardly of said shift register, respectively.
Claim 10
Dependent Claim
37 words
An apparatus as claimed in claim 6, wherein the filter operation of said even-order digital filter is performed in parallel with that of the odd-order digital filter and synchronous with a shift operation of said shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-11 | 1992-04-11 | 1992-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-11 | 1996-04-11 | 1996-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-11 | 2000-04-11 | 2000-10-11 | $7700.00 | Window Closed / Lapsed |