Abstract A field effect transistor having an asymmetric gate includes high dopant concentration source and drain regions. The drain region is shallower and of lower dopant concentration than the source region. The drain is spaced from the gate electrode. Therefore, an ideal FET having a reduced short channel effect and having a lower source resistance and high current drivability (gm) is obtained. When the drain region is produced by ion implantation through a film and the source region is produced by the implantation directly into the substrate, only the drain region is separated from the gate. When the insulating film on the source region is separated from the insulating film on the drain region, the insulating film on the source region is reliably selectively removed, whereby high controllability is obtained.
A Schottky barrier field effect transistor comprising: a compound semiconductor substrate; a doped channel region in said substrate; a gate electrode disposed on said substrate on said channel region and forming a Schottky barrier with said channel region; and a doped source region and a doped drain region disposed in said substrate and spaced apart from each other wherein said source region and said drain region each intersect said channel region and are electrically connected to each other through said channel region, said gate electrode is spaced from said drain region and lies adjacent the intersection of said channel region and said source region, said drain region has a lower dopant concentration than said source region, said channel region has a lower dopant concentration than said drain region, and said drain region is shallower in said substrate than said source region.
Claim 2
Dependent Claim
141 words
A Schottky barrier field effect transistor comprising: a compound semiconductor substrate; a doped channel region in said substrate; a gate electrode disposed on said substrate on said channel region and forming a Schottky barrier with said channel region; and a doped source region and a doped drain region disposed in said substrate and spaced apart from each other wherein said source region and said drain region each intersect said channel region and are electrically connected to each other through said channel region, said gate electrode is spaced from said drain region and lies adjacent the intersection of said channel region and said source region, said drain region has a lower dopant concentration than said source region, said channel region has a lower dopant concentration than said drain region, and said drain region is shallower in said substrate than said source region.