EP0152615A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device and a method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1984-12-21
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Granted: —
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Expires: 2004-12-21
Abstract
Abstract This Schottky barrier gate field effect transistor has N +- type source and drain regions (48, 50) formed in the surface area of a GaAs semi-insulation substrate (30), a channel region (52) formed between the source and drain regions (48, 50), and a gate electrode (47) formed on this channel region (52). Particularly, in this Schottky barrier gate field effect transistor, the gate electrode (47) has a first metal portion (46), which is preferably in Schottky contact with the channel region (52), and a second metal portion (40), which stably affixes to the first metal portion (46). The first and second metal portions (46, 40) are fixed to an insulative portion (44) formed on the channel region (52).
Inventors
- 👤 Tetsuo C/O Patent Division Ishii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 13:38
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D30/80; H10D30/87; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10D64/0126; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/01328; H10D64/0133; H10D64/60; H10D64/64; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
129 words
A semiconductor device comprising a semi-insulation substrate (30), source and drain regions (48, 50; 59, 60) each having a high impurity concentration formed in the surface area of said semi-insulation substrate (30), a channel region (52; 62) having a low impurity concentration formed between said source and drain region (48, 50; 58, 60), gate electrode (47) formed in Schottky contact with said channel region (52; 62) characterized by further comprising an insulative portion (44; 56A, 56B) formed on said channel region (52; 62) and characterized in that said gate electrode (47) is fixed to said insulative portion (44; 56A, 56 B ) and includes a first metal portion (46) formed on said channel region (52; 62) and a second metal portion (40) formed on said first metal portion (46).
Claim 2
Dependent Claim
129 words
A semiconductor device comprising a semi-insulation substrate (30), source and drain regions (48, 50; 59, 60) each having a high impurity concentration formed in the surface area of said semi-insulation substrate (30), a channel region (52; 62) having a low impurity concentration formed between said source and drain region (48, 50; 58, 60), gate electrode (47) formed in Schottky contact with said channel region (52; 62) characterized by further comprising an insulative portion (44; 56A, 56B) formed on said channel region (52; 62) and characterized in that said gate electrode (47) is fixed to said insulative portion (44; 56A, 56 B ) and includes a first metal portion (46) formed on said channel region (52; 62) and a second metal portion (40) formed on said first metal portion (46).
Claim 3
Dependent Claim
37 words
A semiconductor device according to claim 1, characterized in that said insulative portion has a first mask section (44; 56B) which masks the channel region surface between said gate electrode (47) and said drain region (50; 60).
Claim 4
Dependent Claim
36 words
A semiconductor device according to claim 2, characterized in that said insulative portion further has a second mask section (56A) which masks the channel region surface between said gate electrode (47) and said source region (58).
Claim 5
Dependent Claim
20 words
A semiconductor device according to claim 2, characterized in that said semi-insulation substrate (30) is formed of gallium arsenide GaAs.
Claim 6
Dependent Claim
22 words
A semiconductor device according to claim 4, characterized in that said source and drain regions (48, 50; 58, 60) include N-type impurities.
Claim 7
Dependent Claim
27 words
A semiconductor device according to claim 5, characterized in that said first metal portion includes an alloy titanium and tungsten and said second metal portion includes gold.
Claim 8
Independent Claim
179 words
A method of manufacturing a semiconductor device comprising a first step of forming a first region (32) having a low impurity concentration in the surface area of a semi-insulation substrate (30), a second step of forming a gate electrode (47) in Schottky contact with said first region (32), a third step of forming second and third regions (48, 50; 58, 60) each having a high impurity concentration in the surface area of said semi-insulation substrate (30) characterized in that said second step includes a first sub-step of forming a first metal portion (46) on said first region (32) and a second metal portion (40) on said first region (32), characterized by further comprising a fourth step of forming on said first region (32) an insulative portion (44; 56A, 56B) for fixing said first and second metal portions (46, 40), and characterized in that said third step includes a second sub-step of forming said second and third regions (48, 50; 58, 60) using said first and second metal portion (46, 40) and insulative portion (44; 56A, 56B) as the masks.
Claim 9
Independent Claim
179 words
A method of manufacturing a semiconductor device comprising a first step of forming a first region (32) having a low impurity concentration in the surface area of a semi-insulation substrate (30), a second step of forming a gate electrode (47) in Schottky contact with said first region (32), a third step of forming second and third regions (48, 50; 58, 60) each having a high impurity concentration in the surface area of said semi-insulation substrate (30) characterized in that said second step includes a first sub-step of forming a first metal portion (46) on said first region (32) and a second metal portion (40) on said first region (32), characterized by further comprising a fourth step of forming on said first region (32) an insulative portion (44; 56A, 56B) for fixing said first and second metal portions (46, 40), and characterized in that said third step includes a second sub-step of forming said second and third regions (48, 50; 58, 60) using said first and second metal portion (46, 40) and insulative portion (44; 56A, 56B) as the masks.
Claim 10
Dependent Claim
25 words
A method according to claim 7, characterized in that said first step includes a third sub-step of doping N-type impurities into a GaAs semi-insulation substrate.
Claim 11
Dependent Claim
146 words
A method according to claim 8, characterized in that said second step includes: a fourth sub-step of forming a first metal layer (34) on said first region (32); a fifth sub-step of forming on said first metal layer (34) a support layer (36) having a side surface which is substantially perpendicular to the upper surface of said first metal layer (34); a sixth sub-step of covering the surfaces of said support layer (36) and first metal layer (34) by a second metal layer (38); and a seventh sub-step of vertically etching said second and first metal layers (38, 34) toward the upper surface of said first region (32) until the surface of said first region (32) is exposed, thereby allowing the portion of said second metal layer (38) along the side surface of said support layer (36) to be left as the second metal portion (40).
Claim 12
Dependent Claim
100 words
A method according to claim 9, characterized in that said third step includes: an eighth sub-step of covering said support layer (36), second metal portion (40), first metal layer (34), and first region by an insulation layer (42); and a ninth sub-step of etching said insulation layer (42) vertically toward the upper surface of said first region (32) until the surface of said first region (32) is exposed, thereby allowing the portion of said insulation layer (42) along the side surfaces of said second metal portion (40) and first metal layer (34) to be left as said insulative portion (44).
Claim 13
Dependent Claim
84 words
A method according to claim 10, characterized in that said second step includes: a tenth sub-step of removing said support layer (36) from said first metal layer (34) due to a plasma etching process; and an eleventh sub-step of allowing the portion under said second metal portion (40) to be left as the first metal portion (46) and removing said first metal layer (34) from said first region (32) due to a reactive etching process using said second metal portion (40) as the mask.
References Cited (Backward Citations)
No citation records indexed.
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