EP0177129A1
Expired / Lapsed
EP
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Method of manufacturing GaAs field effect transistor
Assignee: Toshiba Corp
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Filing: 1985-07-23
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Granted: —
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Expires: 2005-07-23
Abstract
Abstract According to a manufacturing method of a GaAs FET of this invention, a gate structure (20) is first formed on a GaAs-substrate (10). The gate structure (20) consists of a conductive gate layer (16') and an insulative layer (18'), which are in lateral contact with each other on the substrate (10). Each layer (16' or 18') is isotropically deposited by a CVD process and later anisotropically etched using a RIE process, whereby it has a specific width of the submicron order reduced to an extent substantially equal to an initially deposited thickness thereof. The high frequency property of the GaAs FET can be improved due to the decrease in width of the gate layer (16'). Ion implantation is performed with the gate structure used as a mask to provide in the substrate (10) source and drain regions (22, 24) which are self-aligned with the gate structure (20). The drain regions (24) are removed from the gate layer (16') at a distance equal to the width of the insulative layer (18').
Inventors
- 👤 Toshiyuki C/O Patent Division Terada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 15:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10D30/80; H10D30/87; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10D64/0126; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
181 words
A method for manufacturing a GaAs field effect transistor, characterized in that said method comprises the steps of: forming, on a gallium arsenide substrate (10) involving an operational layer '(12), a gate structure (20, 56) comprising a first layer (16', 54') which is conductive to serve as a gate layer of said transistor and a second layer (18', 52') which is insulative, each of said first and second layers (16', 18'; 54', 52') being isotropically deposited and anisotropically etched and made to have such a width as is reduced to an extent substantially equal to an initial thickness with which it was initially deposited; and performing ion implantation with said gate structure (20, 56) used as a mask to provide in said substrate source and drain regions (22, 24; 58, 60) which are self-aligned with said gate structure (20, 56), said source region (22, 58) being set adjacent to said gate layer (16', 54'), and said drain region (24, 60) being removed from the gate layer (16', 54') at a distance equal to the width of the insulative layer (18', 52').
Claim 2
Independent Claim
181 words
A method for manufacturing a GaAs field effect transistor, characterized in that said method comprises the steps of: forming, on a gallium arsenide substrate (10) involving an operational layer '(12), a gate structure (20, 56) comprising a first layer (16', 54') which is conductive to serve as a gate layer of said transistor and a second layer (18', 52') which is insulative, each of said first and second layers (16', 18'; 54', 52') being isotropically deposited and anisotropically etched and made to have such a width as is reduced to an extent substantially equal to an initial thickness with which it was initially deposited; and performing ion implantation with said gate structure (20, 56) used as a mask to provide in said substrate source and drain regions (22, 24; 58, 60) which are self-aligned with said gate structure (20, 56), said source region (22, 58) being set adjacent to said gate layer (16', 54'), and said drain region (24, 60) being removed from the gate layer (16', 54') at a distance equal to the width of the insulative layer (18', 52').
Claim 3
Dependent Claim
119 words
The method according to claim 1, characterized in that said first layer is deposited through the processes defined below: forming an insulation layer (14) on said substrate (10) with the side wall substantially set upright; uniformly depositing a conductive layer (16) on said substrate (10) and said insulation layer (14) by a process so selected as to cause the deposition to proceed isotropically; anisotropically etching said conductive.layer (16), thereby providing a conductive layer component (16') which is in lateral contact with the vertical side wall of said insulation layer (14); and removing said insulation layer (14) having said vertical side wall, thereby causing a conductive layer component having a substantially vertical side wall to be retained on said substrate.
Claim 4
Dependent Claim
98 words
The method according to claim 2, characterized in that said second layer is deposited through the processes defined below: uniformly depositing an insulative layer (18) on said substrate and conductive layer component by processes selected so as to cause the deposition to proceed isotropically etching said insulative layer (18), thereby providing an insulative layer component (18') set adjacent to the substantially vertical side wall of said conductive layer component; and anisotropically etching said insulative layer (18), thereby providing an insulative layer component (18') which is in lateral contact with the vertical side wall of said conductive layer component.
Claim 5
Dependent Claim
50 words
The method according to claim 2, characterized in that said conductive layer (16) is isotropically formed by a chemical vapor deposition technique, and is later subjected to reactive ion etching, thereby causing said conductive layer component to have a thickness (tl) substantially equal to that of the deposited conductive layer.
Claim 6
Dependent Claim
50 words
The method according to claim 4, characterized in that said insulative layer (18) is isotropically formed by the chemical vapor deposition technique and later processed by reactive ion etching, thereby causing said insulative layer component (18') to have a width (12) substantially equal to that of the deposited insulative layer.
Claim 7
Dependent Claim
110 words
The method according to claim 1, characterized in that said second layer is deposited by the processes defined below: forming a third layer (50) having a substantially vertical side wall on said substrate (10); uniformly depositing an insulative layer (52) on said substrate (10) and said third layer (50) by a process selected so as to cause the deposition to proceed isotropically; anisotropically etching said insulative layer (52), thereby providing an insulative layer component (52') set adjacent to the side wall (50a) of said third layer (50); and removing said third layer (50), thereby retaining an insulative layer component (52') having a substantially vertical side wall on said substrate (10).
Claim 8
Dependent Claim
77 words
The method according to claim 6, characterized in that said first layer is deposited by the processes defined below: uniformly depositing a conductive layer (54) on said substrate (10) and insulative layer component (52') by a process selected so as to cause the deposition to proceed isotropically; and anisotropically etching said conductive layer (54), thereby providing a conductive layer component (54') which is in lateral contact with the side wall (52a) of said insulative layer component (52').
Claim 9
Dependent Claim
48 words
The method according to claim 7, characterized in that said insulative layer (52) is isotropically formed by a chemical deposition technique and later subjected to reactive ion etching, thereby causing said insulative layer component (52') to have a thickness substantially equal to that of the deposited insulative layer.
Claim 10
Dependent Claim
50 words
The method according to claim 8, characterized in that said conductive layer (54) is isotropically formed by the chemical vapor deposition technique, and later subjected to reactive ion etching, thereby causing said conductive layer component (54') to have a width (L2) substantially equal to that of said deposited conductive layer.
References Cited (Backward Citations)
EP0113161A2
Cited
EP0113059A1
Cited
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