Patent US5148527A successfully refreshed from Google Patents.
US5148527A
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Interface for independently establishing a link and transmitting high level commands including logical addresses from dedicated microprocessor to shared intelligent memory
Assignee: Cisco Technology Inc
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Filing: 1989-11-22
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Granted: 1992-09-15
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Expires: 2009-11-22
Abstract
Abstract In a shared memory system, wherein several memory users MU wish access to a plurality of memory banks, a set of high level commands (CREATE, PUT, GET, RELEASE) is provided, to transfer data between a given memory user and the memory banks or another memory user. The high level commands sent by the memory users are built up by memory interfaces MI connected to the memory users, and transmitted through an interconnection network to Packet Memory Command Executors PMCE integrated into each memory bank. The high level commands work with data records identified by Logical Record Addresses (LRA) known by the memory users. During execution of the high level commands by the PMCE, the LRA are translated into physical addresses corresponding to physical address space in the memory banks. The physical address space is created dynamically and released upon need, through the Create or Release Commands. A given memory user is not involved at all by management of physical address space, and works only with the LRA of a record.
Inventors
- 👤 Claude Basso
- 👤 Gerald Lebizay
- 👤 Jean-Marie Munier
- 👤 Andre Pauporte
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:34
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/54; G06F9/544; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1663; G06F9/546
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
254 words
A device for interconnecting processors of a plurality of memory users MU linked through an interconnection network NW to a shared memory PM comprising a plurality of memory banks MB defining a globally shared memory space, said device comprising: means for presenting to said memory banks MB through said network NW a set of high level commands issued by the memory users MU for storing and retrieving records into or from said memory space, said high level commands utilizing only logical addresses (LRA) of said records, and means, physically integrated in each memory bank MB, for retrieving the physical addresses of said records according to their logical addresses LRA and executing said high level commands, and wherein, said means for presenting to said memory banks a set of high level commands, comprises a plurality of memory interfaces MI dedicated to their respective users MU, a given memory interface MI processing each command request from its associated memory user MU by executing the steps of: (a) reading a memory control word MCW including a high level command and a logical address from a user's local memory LM; (b) decoding said high level command; (c) selecting independently one of the memory banks MB; (d) establishing a connection through the interconnection network NW to the selected memory bank MB; (e) sending the high level command including said logical address to said selected memory bank MB; and (f) releasing the connection to said memory bank MB upon receipt of a command response (MSW) from the memory bank MB.
Claim 2
Independent Claim
254 words
A device for interconnecting processors of a plurality of memory users MU linked through an interconnection network NW to a shared memory PM comprising a plurality of memory banks MB defining a globally shared memory space, said device comprising: means for presenting to said memory banks MB through said network NW a set of high level commands issued by the memory users MU for storing and retrieving records into or from said memory space, said high level commands utilizing only logical addresses (LRA) of said records, and means, physically integrated in each memory bank MB, for retrieving the physical addresses of said records according to their logical addresses LRA and executing said high level commands, and wherein, said means for presenting to said memory banks a set of high level commands, comprises a plurality of memory interfaces MI dedicated to their respective users MU, a given memory interface MI processing each command request from its associated memory user MU by executing the steps of: (a) reading a memory control word MCW including a high level command and a logical address from a user's local memory LM; (b) decoding said high level command; (c) selecting independently one of the memory banks MB; (d) establishing a connection through the interconnection network NW to the selected memory bank MB; (e) sending the high level command including said logical address to said selected memory bank MB; and (f) releasing the connection to said memory bank MB upon receipt of a command response (MSW) from the memory bank MB.
Claim 3
Dependent Claim
98 words
A device according to claim 1, wherein said means for retrieving the physical addresses of said records and for executing said high level commands comprises a plurality of subsystem Packet Memory Command Executors PMCE connected and dedicated to their respective memory banks each subsystem PMCE for executing said high level commands sent by a Memory User through a Memory Interface comprises a microprocessor for processing the high level commands and a local storage unit LS for storing said high level commands, said processing being done according to command-depending microprograms located in a program memory associated with said microprocessor.
Claim 4
Dependent Claim
125 words
A device according to claim 2, wherein said means for retrieving the physical addresses of said records according to their logical addresses (LRA) and executing a specific high level commands, include a data memory containing: a plurality of fixed size data buffers; a Logical Record Address Directory for translating a Logical Record Address (LRA) used as a pointer to said directory, into a number of elementary pointers corresponding to a number of physical addresses of data buffers allocated to a record having (LRA) as logical address; a free buffer list FBL wherein a list of data buffers not allocated to a record, is maintained, a free token list FTL wherein a list of the logical record addresses (LRA) not affected to a record, is maintained.
Claim 5
Dependent Claim
113 words
A device according to claim 3, wherein said set of high level commands includes a CREATE command, which, when sent by a memory user MU and memory interface MI to a memory bank MB and executed therein by the corresponding PMCE, comprises the steps of: creating within said memory bank a new record uniquely identified in the Shared Memory PM by a Logical Record Address (LRA) and, returning said Logical Record Address (LRA), in a command response word, to the respective memory interface MI and memory user MU, thus enabling the latter to process the created record by using the logical address (LRA) independently of the physical location of the record in memory.
Claim 6
Dependent Claim
146 words
A device according to claim 3, wherein said set of high level commands includes a PUT command defined by a command code, a Logical Record Address (LRA), a displacement (D), and a variable number N of data bytes to put into data memory after displacement D, said PUT command, when sent by a memory user MU and memory interface MI to a memory bank MB and executed therein by the corresponding PMCE, causing the steps of: allocating to the record specified by the LRA the number of physical data buffers needed to contain the data bytes attached to the specific PUT command; storing said N data bytes into said data buffers; establishing within said memory bank, a LRA directory having one entry per LRA and a given entry including all the elementary pointers for addressing the physical data buffers at a location corresponding to displacement D.
Claim 7
Dependent Claim
135 words
A device according to claim 3, wherein said set of high level commands includes a GET command defined by a command code, a logical record address (LRA), a displacement D, and a number N of data bytes contained in a data memory, said GET command, when sent by a memory user MU and memory interface MI including an LRA directory having pointers for addressing physical memory buffers, to a memory bank MB and executed therein by the corresponding PMCE, causing the steps of: pointing with the LRA to said LRA directory for retrieving said physical addresses of said physical data buffers including said N data bytes after said displacement D; reading said N data bytes; carrying said N data bytes back from said physical data buffer to said memory interface MI and memory user MU.
Claim 8
Dependent Claim
115 words
A device according to claim 3, wherein said set of high level commands includes a RELEASE command defined by a command code and a Logical record address (LRA), said RELEASE command, when sent by a memory user MU and memory interface MI including an LRA directory having pointers for addressing physical data buffers, and a free token list FTC to a memory bank MB and executed therein by the corresponding PMCE, causing the steps of: cancelling the specified logical record address (LRA) from said LRA Directory of the considered memory bank; releasing all physical data buffers pointed at by the content of said specified LRA and, updating the free LRA token list in said FTL.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |