EP0166268A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Shared memory access for data processing system
Assignee: International Business Machines Corp
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Filing: 1985-06-03
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Granted: —
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Expires: 2005-06-03
Abstract
Abstract A plurality of intelligent work stations (10) are provided access to a shared memory (12) through a switching hierarchy including a first array of mapping boxes (14) for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch (16) for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes (18) for receiving the logical address and offset and for I converting the logical address into a memory switch port designation and physical address, and a second switch (20) for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.
Inventors
- 👤 John Cocke
- 👤 Brent Tzion Hailpern
- 👤 Lee Windsor Hoevel
- 👤 Eugene Shapiro
- 👤 Marion Lee Blount
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 21:04
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17375; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0692; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1663
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
214 words
A data processing system including a plurality of intelligent terminals (10), a shared memory (12) and interconnect means for providing access to said shared memory by the intelligent terminals, characterized in that the interconnect means comprises a plurality of first mapping boxes (14) for receiving first addresses from the intelligent terminals, said first addresses including a virtual address and offset, and for converting the virtual addresses to respective terminal switch port designations and logical addresses; a first switch (16) having a plurality of first switch ports coupled to the first mapping boxes and having a plurality of second switch ports, said first switch for forwarding said logical addresses and offsets as second addresses to respective second switch ports corresponding to said terminal switch port designations; a plurality of second mapping boxes (18) for receiving the second addresses and converting the second addresses to respective memory switch port designations and physical addresses; and a second switch (20) having a plurality of first switch ports for receiving said memory switch port designations and physical addresses and having a plurality of second switch ports connected to address inputs of said shared memory, said second switch for forwarding the physical addresses and offsets to respective second ports of the second switch corresponding to said memory switch port designations.
Claim 2
Dependent Claim
214 words
A data processing system including a plurality of intelligent terminals (10), a shared memory (12) and interconnect means for providing access to said shared memory by the intelligent terminals, characterized in that the interconnect means comprises a plurality of first mapping boxes (14) for receiving first addresses from the intelligent terminals, said first addresses including a virtual address and offset, and for converting the virtual addresses to respective terminal switch port designations and logical addresses; a first switch (16) having a plurality of first switch ports coupled to the first mapping boxes and having a plurality of second switch ports, said first switch for forwarding said logical addresses and offsets as second addresses to respective second switch ports corresponding to said terminal switch port designations; a plurality of second mapping boxes (18) for receiving the second addresses and converting the second addresses to respective memory switch port designations and physical addresses; and a second switch (20) having a plurality of first switch ports for receiving said memory switch port designations and physical addresses and having a plurality of second switch ports connected to address inputs of said shared memory, said second switch for forwarding the physical addresses and offsets to respective second ports of the second switch corresponding to said memory switch port designations.
Claim 3
Dependent Claim
34 words
A data processing system as defined in Claim 1, wherein the shared memory (12) comprises a plurality of memory modules each coupled to a respective one of said second ports of the second switch.
Claim 4
Dependent Claim
75 words
A data processing system as defined in Claim 1, wherein each of the first mapping boxes (14) includes translation table means (48) for conversion of a plurality of different virtual addresses to respective combinations of terminal switch port designation and logical address, and wherein each of the second mapping boxes (18) includes translation table means for conversion of a plurality of different logical addresses to respective combinations of memory switch port designation and physical address.
Claim 5
Dependent Claim
155 words
A data processing system as defined in Claim 1, wherein said interconnect means provides each of said intelligent terminals with a plurality of different capabilities, e.g., classes of access, for accessing said shared memory, each first mapping box including at least a first register (50) addressable by a virtual address from its associated intelligent terminal and a translation table (48) of a plurality of capabilities currently available to said associated terminal, said translation table indicating the terminal switch port designation and logical address corresponding to each said capability, said associated intelligent terminal including means for loading into said first register a value representing a requested capability, said first mapping box including conversion means, upon receiving a subsequent first address from said associated intelligent terminal with a virtual address designating said first register, for converting said virtual address to a terminal switch port designation and logical address in accordance with the contents of said first register.
Claim 6
Dependent Claim
75 words
A data processing system as defined in Claim 4, wherein said translation table means in said first mapping box is a partial list of all capabilities currently available to said associated intelligent terminal, said system further including means for maintaining a master list of all capabilities currently available to the associated intelligent terminal, said first mapping box including means for checking the master list when a requested capability is not found in the translation table.
Claim 7
Dependent Claim
124 words
A data processing system as defined in Claim 4, wherein each said intelligent terminal includes means for requesting a capability not currently available to said each intelligent terminal, the system further including processor means (34, 36) responsive to the request for allocating a pretermined area of the shared memory (12) to exercise of said requested capability, the processor means loading into the translation table in one of the second mapping boxes the memory switch port designation and physical address corresponding to the allocated memory area together with the logical address corresponding to the requested capability, and loading into the translation table in the first mapping box a capability designation together with a terminal switch port designation and logical address corresponding to said requested capability.
Claim 8
Dependent Claim
54 words
A data processing system as defined in Claim 1, wherein each said intelligent terminal includes at least a keyboard, monitor and microprocessor (40), and wherein said shared memory, interconnect means and microprocessor are centrally located while said keyboards and monitors of the intelligent terminals are remotely located at physically separate locations from the microprocessors.
References Cited (Backward Citations)
No citation records indexed.
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