Test mode switching system for lsi

Claim 1

A test mode switching system for a large scale integrated circuit, the large scale integrated circuit including data input terminals for applying data signal used in the large scale integrated circuit, control signal input terminals for receiving a signal by which the large scale integrated circuit can be operated, and an address signal input terminal for applying address data to be used in the large scale integrated circuit, the test mode switching system comprising: register means for storing test signal data inputted from an external processing unit through the data input terminals of the large scale integrated circuit, and for outputting the stored test signal data to a self-testing circuit for checking whether or not the large sale integrated circuit is operating correctly; memory means for storing a test inhibiting signal and a test allowing signal received from the an external processing unit through the control signal input terminals of the large scale integrated circuit; and gates means for enabling said register means to output test signals to the self-testing circuit according to a condition of an output of said memory means and a signal applied to the address signal input terminal, thereby allowing the large scale integrated circuit to operate either under a normal operation mode or under a test mode.