EP0087314A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Diagnostic system in a data processor
Assignee: Fujitsu Ltd
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Filing: 1983-02-22
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Granted: —
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Expires: 2003-02-22
Abstract
Abstract In a logical unit provided with a plurality of internal registers (12 to 15; 20), an internal memory (11-1, 11-2; 21) and a combinational circuit (16), such as an arithmetic unit, at least one (13 or 14; 20) of the plurality of internal registers is arranged to be scanned in and out. During diagnosis, when executing an instruction which makes reference to the internal memory (11-1, 11-2; 21), the register than can be scanned in and scanned out is used in place of the internal memory 11-1, 11-2; 21) for diagnosing the combinational circuit (16).
Inventors
- 👤 Katsuhiko C/O Fujitsu Ltd. Patent Dpt. Shioya
- 👤 Tetsuhiko C/O Fujitsu Ltd. Patent Dpt. Ifuku
- 👤 Seiichi C/O Fujitsu Ltd. Patent Dpt. Inamasu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 13:26
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F11/26; G06F11/273; G06F11/2268
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
83 words
A diagnostic system comprising a plurality of internal registers (12 to 15; 20), an internal memory (11-1, 11-2; 21) for storing various data, and a combinational circuit (16), wherein at least one (13 or 14; 20) of the plurality of internal registers is arranged to be scanned in and out; and during diagnosis said one register (13 or 14;20) is used in place of said internal memory (11-1 or 11-2;21) when executing an instruction referring to said internal memory (11-1 or 11-2; 21).
Claim 2
Dependent Claim
83 words
A diagnostic system comprising a plurality of internal registers (12 to 15; 20), an internal memory (11-1, 11-2; 21) for storing various data, and a combinational circuit (16), wherein at least one (13 or 14; 20) of the plurality of internal registers is arranged to be scanned in and out; and during diagnosis said one register (13 or 14;20) is used in place of said internal memory (11-1 or 11-2;21) when executing an instruction referring to said internal memory (11-1 or 11-2; 21).
Claim 3
Dependent Claim
122 words
A system as claimed in claim 1, wherein the said internal memory (21) has input and output gate groups (C to C n , D o to D) such that during diagnosis the internal memory (21) will neither accept data for writing therein in response to a memory write enable signal nor read out data therefrom in response to a memory select signal, and wherein the said one register (20) has input and output gate groups (A o to A n , B 0 to B n ) such that during diagnosis the register (20) will accept data for writing therein in response to a memory write enable signal, and will read out data therefrom in response to a memory select signal.
Claim 4
Dependent Claim
41 words
A system as claimed in claim 1 or 2, wherein the internal registers (12 to 15) are a program counter (12), a flag register (13), a data register (14) and an instruction register (15) of a data processor or logical unit.
Claim 5
Dependent Claim
22 words
A system as claimed in claim 3, wherein the combinational circuit (16) is an arithmetic unit of data processor or logical unit.
References Cited (Backward Citations)
No citation records indexed.
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