EP0255449A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit having a test circuit
Assignee: Fujitsu Ltd
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Filing: 1987-07-30
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Granted: —
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Expires: 2007-07-30
Abstract
Abstract A semiconductor device comprises a test signal generating circuit (12) for generating a test signal having an arbitrary frequency, a first buffer (13) for selectively outputting one of the test signal and an external input signal at least one test circuit (15) supplied with an output signal of the first buffer (13), an external output terminal (30), a logic circuit (14), a second buffer (16) for selectively supplying to the external terminal (30) one of the test signals from the test circuit (15) and an output signal of the logic circuit (14), and a switching 10 signal generating circuit (11) for generating switching signals for the first and second buffers (13,16). The state of the test circuit (15) is checked by use of the test signal to indirectly determine the state of the logic circuit (14).
Inventors
- 👤 Takeshi Sasaki
- 👤 Hideo Monma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 20:18
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
168 words
A semiconductor device comprising: an external input terminal (28) applied with an external input signal; a test signal generating circuit (12) for generating a test signal having an arbitrary frequency; a switching signal generating circuit (11) for generating switching signals; a first buffer (13) for selectively outputting said test signal from said test signal generating circuit (12) in a first mode and said external input signal from said external input terminal (28) in a second mode responsive to said switching signals; at least one test circuit (15) supplied with an output signal of said first buffer (13) in said first mode; an external output terminal (30); a logic circuit (14) supplied with the output signal of said first buffer (13) in said second mode; and a second buffer (16) for selectively supplying to said external terminal (30) the test signal received through said test circuit (15) in said first mode and an output signal of said logic circuit (14) in said second mode responsive to said switching signals.
Claim 2
Dependent Claim
168 words
A semiconductor device comprising: an external input terminal (28) applied with an external input signal; a test signal generating circuit (12) for generating a test signal having an arbitrary frequency; a switching signal generating circuit (11) for generating switching signals; a first buffer (13) for selectively outputting said test signal from said test signal generating circuit (12) in a first mode and said external input signal from said external input terminal (28) in a second mode responsive to said switching signals; at least one test circuit (15) supplied with an output signal of said first buffer (13) in said first mode; an external output terminal (30); a logic circuit (14) supplied with the output signal of said first buffer (13) in said second mode; and a second buffer (16) for selectively supplying to said external terminal (30) the test signal received through said test circuit (15) in said first mode and an output signal of said logic circuit (14) in said second mode responsive to said switching signals.
Claim 3
Dependent Claim
24 words
A semiconductor device as claimed in claim 1, in which said test circuit (15) is located in a vicinity of said logic circuit (14).
Claim 4
Dependent Claim
122 words
A semiconductor device as claimed in claim 1 in which said first buffer (13) comprises a buffer amplifier (27), first gate means (TG₂, TG₃) provided in an input stage of said buffer amplifier (27) for selectively supplying to said buffer amplifier (27) said test signal from said test signal generating circuit (12) in said first mode and said external input signal from said external input terminal (28) in said second mode responsive to said switching signals, and second gate means (TG₄, TG₅) provided in an output stage of said buffer amplifier (27) for selectively supplying an output signal of said buffer amplifier (27) to said test circuit (15) in said first mode and to said logic circuit (14) in said second mode.
Claim 5
Dependent Claim
69 words
A semiconductor device as claimed in claim 1 in which said second buffer (16) comprises a buffer amplifier (29) and gate means (TG₆, TG₇) provided in an input stage of said buffer amplifier (29) for selectively supplying to said external output terminal (30) the test signal received through said test circuit (15) in said first mode and the output signal of said logic circuit (14) in said second mode.
Claim 6
Dependent Claim
71 words
A semiconductor device as claimed in claim 1, in which said test signal generating circuit (12) comprises first and second voltage controlled oscillators (24,25) supplied with a control voltage, and a NAND circuit (26) supplied with output signals of said first and second voltage controlled oscillators (24,25) for producing said test signal, said first and second voltage controlled oscillators (24,25, having mutually different input control voltage versus output oscillation frequency characteristics.
Claim 7
Dependent Claim
30 words
A semiconductor device as claimed in claim 5 which further comprises a voltage supply circuit (35) for supplying said control voltage to said first and second voltage controlled oscillators (24,25).
Claim 8
Dependent Claim
29 words
A semiconductor device as claimed in claim 6 in which said voltage supply circuit (35) supplies a variable control voltage to variably control the frequency of said test signal.
References Cited (Backward Citations)
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