Patent US4512864A successfully refreshed from Google Patents.
US5142223A
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US
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Device for testing semiconductor device
Assignee: Mitsubishi Electric Corp
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Filing: 1991-03-05
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Granted: 1992-08-25
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Expires: 2011-03-05
Abstract
Abstract A testing device comprises a plurality of pin test portions, each of which is separately provided with a pin pattern controller for controlling the readout of pattern and timing data from pattern and timing memories and a pin instruction memory for storing programs defining the operation procedure of the pin pattern controller. Therefore, the data to be stored in the pattern and timing memories in each of the pin test portions can be in a compressed form, independently of the data to be stored in the pattern and timing memories in the other pin test portions.
Inventors
- 👤 Naomi Higashino
- 👤 Ryuji Omura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
178 words
A device for testing a semiconductor device having a plurality of pins, comprising: a plurality of external signal terminals to be connected to said pins; and a plurality of pin test portions provided correspondingly to said external signal terminals, respectively, each of said pin test portions comprising: first storing means for storing first data on logical patterns of a test signal to be applied through a corresponding one of said external signal terminals to a corresponding one of said pins to which the external signal terminal is connected; second storing means for storing second data on timings in which said test signal is applied; control means for controlling readout of said first and second data from said first and second storing means; third storing means for storing programs which specify an operation process of said control means; and signal generating means for generating said test signal on the basis of said first and second data which are read out from said first and second storing means to apply it to a corresponding one of said external signal terminals.
Claim 2
Independent Claim
178 words
A device for testing a semiconductor device having a plurality of pins, comprising: a plurality of external signal terminals to be connected to said pins; and a plurality of pin test portions provided correspondingly to said external signal terminals, respectively, each of said pin test portions comprising: first storing means for storing first data on logical patterns of a test signal to be applied through a corresponding one of said external signal terminals to a corresponding one of said pins to which the external signal terminal is connected; second storing means for storing second data on timings in which said test signal is applied; control means for controlling readout of said first and second data from said first and second storing means; third storing means for storing programs which specify an operation process of said control means; and signal generating means for generating said test signal on the basis of said first and second data which are read out from said first and second storing means to apply it to a corresponding one of said external signal terminals.
Claim 3
Dependent Claim
46 words
A device for testing a semiconductor device in accordance with claim 1, further comprising common control means for controlling functions in relation to all of said pin test portions, and fourth storing means for storing programs which define an operation procedure of said common control means.
Claim 4
Dependent Claim
134 words
A device for testing a semiconductor device in accordance with claim 2, wherein said programs of said fourth storing means include a labelled instruction which is related to a control common to all of said pin test portions, said common control means transmitting label data to each of said pin test portions in response to said labelled instruction, each of said pin test portions further comrpising fifth storing means for storing a table indicating correspondence between contents of said label data and specific addresses of said third storing means, said control means accessing said fifth storing means in response to said label data transmitted from said common control means to obtain an address corresponding to said label data to operate in accordance with a content in said address obtained of said third storing means.
Claim 5
Dependent Claim
78 words
A device for testing a semiconductor device in accordance with claim 2, further comprising sixth storing means for storing period data which define a period of a test synchronizing signal for synchronizing each of said pin test portions with each other and for outputting said period data under control of said common control means, and a test synchronizing signal generator for generating said test synchronizing signal in accordance with said period data output from said sixth storing means.
Claim 6
Dependent Claim
93 words
A device for testing a semiconductor device in accordance with claim 1, wherein said first storing means also stores third data on logical patterns of judgment, and said second storing means also stores fourth data on timings of performing said judgment, each of said pin test portions further comprising judging means for judging correctness of a response output signal applied form said semiconductor device through a corresponding one of said external signal terminals on the basis of said third and fourth data which are read out from said first and second storing means.
Claim 7
Dependent Claim
45 words
A device for testing a semiconductor device in accordance with claim 5, wherein each of said pin test portions further comprising a timing generator for generating a timing signal on the basis of said second and fourth data read out from said second storing means.
Claim 8
Dependent Claim
58 words
A device for testing a semiconductor device in accordance with claim 6, wherein said signal generating means includes an output waveform generation circuit for generating an output waveform on the basis of said first data read out from said frist storing means and said timing signal generated by said timing generator to output it as said test signal.
Claim 9
Dependent Claim
58 words
A device for testing a semiconductor device in accordance with claim 7, wherein said judging means includes a comparator for sampling said response output signal in timing of said timing signal output from said timing generator to make a judgment by comparing said response output signal as sampled with said third data output from said first storing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-25 | 1996-02-24 | 1996-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-25 | 2000-02-24 | 2000-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-25 | 2004-02-24 | 2004-08-25 | $7700.00 | Window Closed / Lapsed |