US3622876A
Expired / Lapsed
US
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Digital module tester system
Assignee: Datatron Inc
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Filing: 1970-12-14
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Granted: 1971-11-23
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Expires: 1990-12-14
Abstract
Abstract A digital module tester system for dynamically testing multipin digital circuit modules in which a separate programmable pin electronics card is provided for each pin of the module under test. A computer controls a single digital-to-analog converter to continuously update the drive level and monitoring limits of each pin electronics card. Each pin electronics card contains switching circuitry to permit operation in a voltage forcing or current forcing mode. In the voltage forcing mode, a pin driver differential amplifier forces a voltage at the pin under test. A precision resistor in series with the pin driver differential amplifier and the pin under test is monitored for current flow to the pin under test. Comparison circuitry compares the current flow with limit levels to provide an error indication in the event that the limits are exceeded. In the current forcing mode the pin driver differential amplifier provides a fixed current flow into the pin under test. The voltage at the pin under test is monitored and compared with limit levels to provide an error indication.
Inventors
- 👤 Gary Ross Ure
- 👤 Donald Lee Degraffenreid
- 👤 Robert Allen Savage
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 17:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31924
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
657 words
A pin electronics circuit for use in a computer controlled digital circuit module tester in which drive signals for voltage or current forcing are impressed on individual pins of multipin modules, the response at individual pins is compared with predetermined limits, and the drive levels and limit levels are provided by an analog source comprising, in combination; a first switch having two sides and a control input and having one side connected to the analog source to receive a signal representing the level for a logic one, and the control input connected to the computer; a second switch having two sides and a control input and having one side connected to the analog source to receive a signal representing the level for a logic zero, and the control input connected to the computer; a first sample and hold amplifier having an input and an output and having the input connected to the output of the first switch and maintaining an output signal equal in amplitude to that of the signal appearing at the input terminal: a second sample and hold amplifier having an input and an output and having the input connected to the output of the second switch and maintaining an output signal equal in amplitude to that of the signal appearing at the input terminal; a third switch having first and second sides and a control input and having the first side connected to the output of the first sample and hold amplifier and the control input connected to the computer to receive the data signal representative of a logic one or a logic zero forcing condition which causes the switch to close when a logic one condition is selected and to open when a logic zero condition is selected; a fourth switch having first and second sides and a control input and having the first side connected to the output of the second sample and hold amplifier, and the second side connected to the second side of the third switch, and the control input connected to the computer to receive a data signal representative of a logic one forcing or a logic zero forcing condition to close the switch for a logic zero condition and open it for a logic one; a pin driver differential amplifier circuit having first and second inputs and an output, operating to increase the level of the output signal whenever the level of the input signal to the second input is lower than the level of the input signal to the first input and having the first input connected to the second sides of the third and fourth switches; an output terminal for connection to the pin of the circuit module under test; a plurality of fixed precision resistors; first switch means connected to the computer for connecting selected combinations of the fixed resistors in series with the pin driver differential amplifier circuit output and the output terminal; first differential amplifier having first and second inputs and an output and having the first input connected to the output terminal and the second input connected to the output of the pin driver differential amplifier circuit; a sense terminal coupled to the pin of the circuit under test; a fifth switch having first and second sides and a control input and having the first side connected to the sense terminal and the second side connected to the second input of the pin driver differential amplifier circuit, and the control input connected to the computer to receive a signal representative of the voltage or current forcing mode of operation; a sixth switch having first and second sides and a control input and having the first side connected to the output of the first differential amplifier, the second side connected to the second input of the pin driver differential amplifier circuit, and the control input connected to the computer to receive a signal representative of the voltage or current forcing mode of operation.
Claim 2
Dependent Claim
657 words
A pin electronics circuit for use in a computer controlled digital circuit module tester in which drive signals for voltage or current forcing are impressed on individual pins of multipin modules, the response at individual pins is compared with predetermined limits, and the drive levels and limit levels are provided by an analog source comprising, in combination; a first switch having two sides and a control input and having one side connected to the analog source to receive a signal representing the level for a logic one, and the control input connected to the computer; a second switch having two sides and a control input and having one side connected to the analog source to receive a signal representing the level for a logic zero, and the control input connected to the computer; a first sample and hold amplifier having an input and an output and having the input connected to the output of the first switch and maintaining an output signal equal in amplitude to that of the signal appearing at the input terminal: a second sample and hold amplifier having an input and an output and having the input connected to the output of the second switch and maintaining an output signal equal in amplitude to that of the signal appearing at the input terminal; a third switch having first and second sides and a control input and having the first side connected to the output of the first sample and hold amplifier and the control input connected to the computer to receive the data signal representative of a logic one or a logic zero forcing condition which causes the switch to close when a logic one condition is selected and to open when a logic zero condition is selected; a fourth switch having first and second sides and a control input and having the first side connected to the output of the second sample and hold amplifier, and the second side connected to the second side of the third switch, and the control input connected to the computer to receive a data signal representative of a logic one forcing or a logic zero forcing condition to close the switch for a logic zero condition and open it for a logic one; a pin driver differential amplifier circuit having first and second inputs and an output, operating to increase the level of the output signal whenever the level of the input signal to the second input is lower than the level of the input signal to the first input and having the first input connected to the second sides of the third and fourth switches; an output terminal for connection to the pin of the circuit module under test; a plurality of fixed precision resistors; first switch means connected to the computer for connecting selected combinations of the fixed resistors in series with the pin driver differential amplifier circuit output and the output terminal; first differential amplifier having first and second inputs and an output and having the first input connected to the output terminal and the second input connected to the output of the pin driver differential amplifier circuit; a sense terminal coupled to the pin of the circuit under test; a fifth switch having first and second sides and a control input and having the first side connected to the sense terminal and the second side connected to the second input of the pin driver differential amplifier circuit, and the control input connected to the computer to receive a signal representative of the voltage or current forcing mode of operation; a sixth switch having first and second sides and a control input and having the first side connected to the output of the first differential amplifier, the second side connected to the second input of the pin driver differential amplifier circuit, and the control input connected to the computer to receive a signal representative of the voltage or current forcing mode of operation.
Claim 3
Dependent Claim
594 words
The appAratus as described in claim 1 including: seventh, eighth, ninth and tenth switches each having first and second sides and a control input, each having the first side connected to the analog source and having the control input connected to the computer to receive signals representative of a logic one upper limit level, logic one lower limit level, logic zero upper limit level and logic zero lower limit level respectively; third, fourth, fifth and sixth sample and hold amplifiers each having an input and an output and having the inputs connected to the other side of the seventh, eighth, ninth and 10th switches respectively; an 11th switch having first and second sides and a control input and having the first side connected to the output of the third sample and hold amplifier; a 12th switch having first and second inputs and a control input and having the first side connected to the output of the fourth sample and hold amplifier; the control inputs of the 11th and 12th switches connected to the computer to receive a data switch signal representative of a logic one or a logic zero forcing condition which causes the 11th and 12th switches to close when logic one condition is selected and to open when a logic zero condition is selected; a 13th switch having first and second sides and a control input and having the first side connected to the output of the fifth sample and hold amplifier; a 14th switch having first and second sides and a control input and having the first side connected to the output of the sixth sample and hold amplifier; the control inputs of the 13th and 14th switches connected to the computer to receive a data switch signal representative of a logic one or a logic zero forcing condition which causes the 13th and 14th switches to close when a logic zero condition is selected and to open when a logic one condition is selected; a 15th switch having first and second sides and a control input and having the first side connected to the sense terminal; a 16th switch having first and second sides and a control input and having the first side connected to the second side of the 15th switch and the second side connected to the output of the first differential amplifier; the control inputs for the 15th and 16th switches connected to the computer to receive a signal representative of the voltage or current forcing mode of operation such that in the voltage forcing mode of operation the 15th switch is closed and the 16th switch is open and in the current forcing mode of operation the 15th switch is open and the 16th switch is closed; a second differential amplifier having first and second inputs and an output and having the first input connected to the second side of the 15th switch and the second input connected to the second side of the 12th and 14th switches; a third differential amplifier having first and second inputs and an output and having the first input connected to the second side of the 13th switch and the second input connected to the second side of the 15th switch; an OR gate having first and second inputs and an output and having the first input connected to the output of the second differential amplifier and the second input connected to the output of the third differential amplifier; and the output of the OR gate connected to an error output terminal for providing a signal representative of any error.
Claim 4
Dependent Claim
53 words
The apparatus as described in claim 2 including a bistable multivibrator circuit having an input and an output; and the bistable multivibrator circuit connected between the OR gate output and the error output terminal having the input connected to the output of the OR gate and the output connected to the error terminal.
Claim 5
Dependent Claim
646 words
A pin electronics circuit for use in a computer controlled digital circuit module tester in which drive signals for voltage or current forcing are impressed on individual pins of multipin modules and the response at individual pins is compared with predetermined limits with the drive levels and limit levels provided by an analog source comprising, in combination: first switching means coupled to the analog source and to the computer for receiving analog signals from the analog source representative of the levels for a logic one, logic zero, logic one upper limit, logic one lower limit, logic zero upper limit and logic zero lower limit and sequenting commands from the computer; sample and hold means coupled to the first switching means for sequentially receiving the analog level signals from the analog source in accordance with the sequenting controls for storing these levels, and for providing output signals representative of the levels receiver; a pin driver means having first and second inputs and an output operating to increase the level of the output signal whenever the level of the input signal to the second input is lower than the level of the input signal to the first input; second switching means connected to sample and hold means, to the first input of the pin driver means and the computer to switch under computer control a level signal representative of a logic one or a logic zero into the first input of the pin driver means; an output terminal for connection to the pin of the circuit module under test; a plurality of fixed resistors; third switching means connected to the computer and the fixed resistor for selectively connecting combinations of the fixed resistors in series with the pin driver means output and the output terminal; a sense line coupled to the pin of the circuit module under test; amplifier means having first and second inputs and an output and having the first input connected to the output terminal and the second input connected to the output of the pin driver means; a first switch having first and second sides and a control input and having the first side connected to the sense line and the second side connected to the second input of the pin driver means; a second switch having first and second sides and a control input and having the first side connected to the output of the amplifier means and the second side connected to the second input of the pin driver means; the control inputs of the first and second switches connected to the computer to receive signals representative of a voltage or current forcing mode of operation such that in the voltage forcing mode the first switch is open and the second switch is closed and in the current forcing mode the first switch is closed and the second switch is open; comparison circuitry for comparing the logic one and logic zero signal levels monitored at the pin under test with the logic level limits from the analog source; third switching means connected to the sample and hold means, the comparison circuit and to the computer to couple under computer control the logic one upper and lower limits to the comparison circuitry during the logic one forcing conditions and to connected the logic zero upper and lower limits levels to the comparison circuitry during the logic zero forcing condition; and fourth switching means connected to the sense line, the output of the amplifier means, the comparison circuitry, and the computer for connecting the sense line to the comparison circuit and the amplifier means output to the second input of the pin driver means during the current forcing mode of operation and for connecting the output of the amplifier means to the comparison circuit and the sense line to the second input of the pin driver means during the current forcing mode of operation.
Claim 6
Dependent Claim
646 words
A pin electronics circuit for use in a computer controlled digital circuit module tester in which drive signals for voltage or current forcing are impressed on individual pins of multipin modules and the response at individual pins is compared with predetermined limits with the drive levels and limit levels provided by an analog source comprising, in combination: first switching means coupled to the analog source and to the computer for receiving analog signals from the analog source representative of the levels for a logic one, logic zero, logic one upper limit, logic one lower limit, logic zero upper limit and logic zero lower limit and sequenting commands from the computer; sample and hold means coupled to the first switching means for sequentially receiving the analog level signals from the analog source in accordance with the sequenting controls for storing these levels, and for providing output signals representative of the levels receiver; a pin driver means having first and second inputs and an output operating to increase the level of the output signal whenever the level of the input signal to the second input is lower than the level of the input signal to the first input; second switching means connected to sample and hold means, to the first input of the pin driver means and the computer to switch under computer control a level signal representative of a logic one or a logic zero into the first input of the pin driver means; an output terminal for connection to the pin of the circuit module under test; a plurality of fixed resistors; third switching means connected to the computer and the fixed resistor for selectively connecting combinations of the fixed resistors in series with the pin driver means output and the output terminal; a sense line coupled to the pin of the circuit module under test; amplifier means having first and second inputs and an output and having the first input connected to the output terminal and the second input connected to the output of the pin driver means; a first switch having first and second sides and a control input and having the first side connected to the sense line and the second side connected to the second input of the pin driver means; a second switch having first and second sides and a control input and having the first side connected to the output of the amplifier means and the second side connected to the second input of the pin driver means; the control inputs of the first and second switches connected to the computer to receive signals representative of a voltage or current forcing mode of operation such that in the voltage forcing mode the first switch is open and the second switch is closed and in the current forcing mode the first switch is closed and the second switch is open; comparison circuitry for comparing the logic one and logic zero signal levels monitored at the pin under test with the logic level limits from the analog source; third switching means connected to the sample and hold means, the comparison circuit and to the computer to couple under computer control the logic one upper and lower limits to the comparison circuitry during the logic one forcing conditions and to connected the logic zero upper and lower limits levels to the comparison circuitry during the logic zero forcing condition; and fourth switching means connected to the sense line, the output of the amplifier means, the comparison circuitry, and the computer for connecting the sense line to the comparison circuit and the amplifier means output to the second input of the pin driver means during the current forcing mode of operation and for connecting the output of the amplifier means to the comparison circuit and the sense line to the second input of the pin driver means during the current forcing mode of operation.
Claim 7
Dependent Claim
20 words
The apparatus a claimed in claim 4 wherein the sense line is coupled through a resistor to the output terminal.
Claim 8
Dependent Claim
32 words
The apparatus as claimed in claim 4 wherein the sample and hold means comprises: a plurality of indiVidual sample and hold amplifiers each adapted to receive and store a separate level signal.
Claim 9
Dependent Claim
623 words
A pin electronics circuit for use in a computer controlled digital circuit module tester in which drive signals for voltage or current forcing are impressed on individual pins of multipin modules and the response at individual pins is compared with predetermined limits with the drive levels and limit levels provided by an analog source comprising, in combination: first switching means coupled to the analog source and to the computer for receiving analog signals from the analog source representative of logic levels and the limits for the levels and sequencing commands from the computer; sample and hold means coupled to the first switching means for sequentially receiving the analog level signals from the analog source in accordance with the sequenting controls for storing these levels, and for providing output signals representative of the levels received; a pin driver means having first and second inputs and an output operating to increase the level of the output signal whenever the level of the input signal to the second input is lower than the level of the input signal to the first input; second switching means connected to sample and hold means, to the first input of the pin driver means and the computer to switch under computer control a level signal representative of a logic one or a logic zero into the first input of the pin driver means; an output terminal for connection to the pin of the circuit module under test; a plurality of fixed resistors; third switching means connected to the computer and the fixed resistors for selectively connecting combinations of the fixed resistors in series with the pin driver means output and the output terminal; a sense line coupled to the pin of the circuit module under test; amplifier means having first and second inputs and an output and having the first input connected to the output terminal and the second input connected to the output of the pin driver means; a first switch having first and second sides and a control input and having the first side connected to the sense line and the second side connected to the second input of the pin driver means; a second switch having first and second sides and a control input and having the first side connected to the output of the amplifier means and the second side connected to the second input of the pin driver means; the control inputs of the first and second switches connected to the computer to receive signals representative of a voltage or current forcing mode of operation such that in the voltage forcing mode the first switch is open and the second switch is closed and in the current forcing mode the first switch is closed and the second switch is open; comparison circuitry for comparing the logic one and logic zero signal levels monitored at the pin under test with the logic level limits from the analog source; third switching means connected to the sample and hold means, the comparison circuit and to the computer to couple under computer control the logic one limits to the comparison circuitry during the logic one forcing condition and to connect the logic zero limits levels to the comparison circuitry during the logic zero forcing condition; and fourth switching means connected to the sense line, the output of the amplifier means, the comparison circuitry, and the computer for connecting the sense line to the comparison circuit and the amplifier means output to the second input of the pin driver means during the current forcing mode of operation and for connecting the output of the amplifier means to the comparison circuit and the sense line to the second input of the pin driver means during the current forcing mode of operation.
Claim 10
Dependent Claim
623 words
A pin electronics circuit for use in a computer controlled digital circuit module tester in which drive signals for voltage or current forcing are impressed on individual pins of multipin modules and the response at individual pins is compared with predetermined limits with the drive levels and limit levels provided by an analog source comprising, in combination: first switching means coupled to the analog source and to the computer for receiving analog signals from the analog source representative of logic levels and the limits for the levels and sequencing commands from the computer; sample and hold means coupled to the first switching means for sequentially receiving the analog level signals from the analog source in accordance with the sequenting controls for storing these levels, and for providing output signals representative of the levels received; a pin driver means having first and second inputs and an output operating to increase the level of the output signal whenever the level of the input signal to the second input is lower than the level of the input signal to the first input; second switching means connected to sample and hold means, to the first input of the pin driver means and the computer to switch under computer control a level signal representative of a logic one or a logic zero into the first input of the pin driver means; an output terminal for connection to the pin of the circuit module under test; a plurality of fixed resistors; third switching means connected to the computer and the fixed resistors for selectively connecting combinations of the fixed resistors in series with the pin driver means output and the output terminal; a sense line coupled to the pin of the circuit module under test; amplifier means having first and second inputs and an output and having the first input connected to the output terminal and the second input connected to the output of the pin driver means; a first switch having first and second sides and a control input and having the first side connected to the sense line and the second side connected to the second input of the pin driver means; a second switch having first and second sides and a control input and having the first side connected to the output of the amplifier means and the second side connected to the second input of the pin driver means; the control inputs of the first and second switches connected to the computer to receive signals representative of a voltage or current forcing mode of operation such that in the voltage forcing mode the first switch is open and the second switch is closed and in the current forcing mode the first switch is closed and the second switch is open; comparison circuitry for comparing the logic one and logic zero signal levels monitored at the pin under test with the logic level limits from the analog source; third switching means connected to the sample and hold means, the comparison circuit and to the computer to couple under computer control the logic one limits to the comparison circuitry during the logic one forcing condition and to connect the logic zero limits levels to the comparison circuitry during the logic zero forcing condition; and fourth switching means connected to the sense line, the output of the amplifier means, the comparison circuitry, and the computer for connecting the sense line to the comparison circuit and the amplifier means output to the second input of the pin driver means during the current forcing mode of operation and for connecting the output of the amplifier means to the comparison circuit and the sense line to the second input of the pin driver means during the current forcing mode of operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-22 | 1975-05-24 | 1975-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-22 | 1979-05-24 | 1979-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-22 | 1983-05-24 | 1983-11-23 | $7700.00 | Window Closed / Lapsed |