US5141898A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with means for reducing ESD damage
Assignee: Analog Devices Inc
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Filing: 1991-09-27
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Granted: 1992-08-25
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Expires: 2011-09-27
Abstract
Abstract An integrated-circuit (IC) chip having means to prevent or mitigate damage from electrostatic discharge (ESD) employing a thick dielectric coating of insulative oxide between the surface of the chip substrate and the metallization film used to make contact with regions of the substrate. At least a portion of this layer is formed at temperatures below 700° C. The coating is sufficiently thick everywhere that its breakdown voltage is greater than the breakdown voltage of any junction in the substrate. This assures that the breakdown caused by ESD will always occur in the junction, which is self healing, rather than in the dielectric coating, where the damage could be permanent.
Inventors
- 👤 Jerome F. Lapham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:03
CPC Classifications
H; H10; H10W; H10W42/00; H10W42/60; H10D; H10D89/00; H10D89/60
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
230 words
The method of making a monolithic chip of a type having an integrated circuit comprising a multiplicity of transistor circuit elements each having at least one p/n junction, said chip being resistant to damage from electrostatic discharge without the provision of any protection device separate from or additional to said transistor circuit elements of said integrated circuit, comprising the steps of: providing a semiconductive substrate with impurities to form doped regions establishing said multiplicity of transistor circuit elements with junctions, said circuit elements when interconnected together forming said integrated circuit; growing high temperature dielectric over said substrate as part of the integrated circuit forming process; depositing low-temperature dielectric over said substrate, said low-temperature dielectric being of sufficient thickness that said substrate is formed with dielectric material having a total thickness providing a dielectric breakdown voltage greater than the breakdown voltage of any of said circuit element junctions; and forming a metal interconnect layer over said low-temperature dielectric and including a portion making electrical connection to at least one of said doped regions establishing said junctions, said low-temperature dielectric being positioned to lie under said metal interconnect layer at all portions thereof needing a build-up of dielectric thickness to reach said total thickness, whereby an electrostatic discharge from said metal interconnect will pass through and break down a junction of one of said transistor circuit elements rather than said dielectric material.
Claim 2
Independent Claim
230 words
The method of making a monolithic chip of a type having an integrated circuit comprising a multiplicity of transistor circuit elements each having at least one p/n junction, said chip being resistant to damage from electrostatic discharge without the provision of any protection device separate from or additional to said transistor circuit elements of said integrated circuit, comprising the steps of: providing a semiconductive substrate with impurities to form doped regions establishing said multiplicity of transistor circuit elements with junctions, said circuit elements when interconnected together forming said integrated circuit; growing high temperature dielectric over said substrate as part of the integrated circuit forming process; depositing low-temperature dielectric over said substrate, said low-temperature dielectric being of sufficient thickness that said substrate is formed with dielectric material having a total thickness providing a dielectric breakdown voltage greater than the breakdown voltage of any of said circuit element junctions; and forming a metal interconnect layer over said low-temperature dielectric and including a portion making electrical connection to at least one of said doped regions establishing said junctions, said low-temperature dielectric being positioned to lie under said metal interconnect layer at all portions thereof needing a build-up of dielectric thickness to reach said total thickness, whereby an electrostatic discharge from said metal interconnect will pass through and break down a junction of one of said transistor circuit elements rather than said dielectric material.
Claim 3
Dependent Claim
82 words
The method of claim 1, wherein said dielectric material on said substrate includes two distinct layers, one being said layer of high-temperature dielectric, and the other being said layer of low-temperature dielectric laid down over said layer of high-temperature dielectric, said two layers being in contact in at least certain regions thereof and having a combined thickness in all regions thereof beneath said interconnect layer sufficient to create a dielectric breakdown voltage greater than the breakdown voltage of any of said junctions.
Claim 4
Dependent Claim
34 words
The method of claim 2, wherein said high-temperature dielectric layer is thermally grown at a temperature greater than 700° C; and said low-temperature dielectric layer is deposited at a temperature less than 700° C.
Claim 5
Dependent Claim
14 words
The method of claim 1, wherein said low and high temperature dielectric comprises oxides.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-25 | 1996-02-24 | 1996-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-25 | 2000-02-24 | 2000-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-25 | 2004-02-24 | 2004-08-25 | $7700.00 | Window Closed / Lapsed |