Thin polysilicon resistors

Claim 1

A method of forming a resistor in a layer of polycrystalline silicon comprising the steps of: depositing a layer of polycrystalline silicon above a silicon substrate with an initial layer thickness and an initial layer dopant concentration and having an initial layer etch rate for a predetermined etching method; etching a predetermined resistor area of said layer to a resistor thickness less than said initial layer thickness; covering said resistor area with a protective coating for blocking implanted ions; implanting that portion of said layer of polycrystalline silicon outside said protective coating with a connection implant of predetermined interconnection dopant magnitude to form an interconnection area of said poly layer, whereby said interconnection area has an interconnection etch rate and an interconnection etch end point for said initial layer thickness and for said predetermined etching method, said resistor layer thickness and said predetermined initial layer etch rate determine a resistor etch end point and are related to said initial layer thickness and said interconnection etch rate such that said interconnection etch end point and said resistor etch end point are substantially equal; patterning said layer of polycrystalline silicon to define said resistor; and etching said layer to form said resistor.

Claim 2

A method of forming a resistor in a layer of polycrystalline silicon comprising the steps of: depositing a layer of polycrystalline silicon above a silicon substrate with an initial layer thickness and an initial layer dopant concentration and having an initial layer etch rate for a predetermined etching method; etching a predetermined resistor area of said layer to a resistor thickness less than said initial layer thickness; covering said resistor area with a protective coating for blocking implanted ions; implanting that portion of said layer of polycrystalline silicon outside said protective coating with a connection implant of predetermined interconnection dopant magnitude to form an interconnection area of said poly layer, whereby said interconnection area has an interconnection etch rate and an interconnection etch end point for said initial layer thickness and for said predetermined etching method, said resistor layer thickness and said predetermined initial layer etch rate determine a resistor etch end point and are related to said initial layer thickness and said interconnection etch rate such that said interconnection etch end point and said resistor etch end point are substantially equal; patterning said layer of polycrystalline silicon to define said resistor; and etching said layer to form said resistor.