Spurious interrupt monitor

Claim 2

A microprocessor system comprising: a communication bus which performs a plurality of bus cycles, including interrupt acknowledge bus cycles; interrupt processing apparatus responsive to interrupt priority level signals carried by the communication bus; an interrupt arbitration apparatus responsive to interrupt arbitration signals carried by the communication bus; bus error means coupled to the communication bus for generating a bus error signal a predetermined length of time after a bus cycle has commenced unless one of one or more predetermined bus signals becomes active before the predetermined length of time has passed; first logic means coupled to the communication bus and to the bus error means for generating the bus error signal during a predetermined portion of interrupt acknowledge bus cycles, which predetermined portion occurs prior to expiration of the predetermined length of time, unless an inhibit signal is applied to an inhibit input of the first logic means prior to the predetermined portion of the interrupt acknowledge cycle; and second logic means coupled to receive the interrupt arbitration signals from the communication bus and having an output coupled to the inhibit input of the first logic means for producing the inhibit signal upon receiving any of the interrupt arbitration signals.

Claim 3

A microprocessor system according to claim 1 wherein the second logic means further comprises: a latch having inputs coupled to receive the interrupt arbitration signals.

Claim 4

A microprocessor system according to claim 2 wherein the interrupt arbitration signals are carried on multiple lines of the communication bus in bit-serial fashion and the latch further comprises: a set-reset latch having the interrupt arbitration signal connected to a reset input of the set-reset latch and a true output of the set-reset latch connected to the inhibit input of the first logic means.

Claim 5

A microprocessor system comprising: a communication bus; a central processing unit coupled to the communication bus and capable of operating the communication bus as a bus master to perform a plurality of bus cycles, including interrupt acknowledge bus cycles, the central processing unit is also responsive to interrupt priority level signals carried by the communication bus; an interrupt arbitration apparatus responsive to interrupt arbitration signals carried by the communication bus; bus error means coupled to the communication bus for generating a bus error signal a predetermined length of time after a bus cycle has commenced unless one of one or more predetermined bus signals becomes active before the predetermined length of time has passed; first logic means coupled to the communication bus and to the bus error means for generating the bus error signal during a predetermined portion of interrupt acknowledge bus cycles, which predetermined portion occurs prior to expiration of the predetermined length of time, unless an inhibit signal is applied to an inhibit input of the first logic means prior to the predetermined portion of the interrupt acknowledge cycle; and second logic means coupled to receive the interrupt arbitration signals from the communication bus and having an output coupled to the inhibit input of the first logic means for producing the inhibit signal upon receiving any of the interrupt arbitration signals.

Claim 6

A microprocessor system comprising: a communication bus; a central processing unit coupled to the communication bus and capable of operating the communication bus as a bus master to perform a plurality of bus cycles, including interrupt acknowledge bus cycles, the central processing unit is also responsive to interrupt priority level signals carried by the communication bus; an interrupt arbitration apparatus responsive to interrupt arbitration signals carried by the communication bus; bus error means coupled to the communication bus for generating a bus error signal a predetermined length of time after a bus cycle has commenced unless one of one or more predetermined bus signals becomes active before the predetermined length of time has passed; first logic means coupled to the communication bus and to the bus error means for generating the bus error signal during a predetermined portion of interrupt acknowledge bus cycles, which predetermined portion occurs prior to expiration of the predetermined length of time, unless an inhibit signal is applied to an inhibit input of the first logic means prior to the predetermined portion of the interrupt acknowledge cycle; and second logic means coupled to receive the interrupt arbitration signals from the communication bus and having an output coupled to the inhibit input of the first logic means for producing the inhibit signal upon receiving any of the interrupt arbitration signals.

Claim 7

A microprocessor system according to claim 4 wherein the second logic means further comprises: a latch having inputs coupled to receive the interrupt arbitration signals.

Claim 8

A microprocessor system according to claim 5 wherein the interrupt arbitration signals are carried on multiple lines of the communication bus in bit-serial fashion and the latch further comprises: a set-reset latch having the interrupt arbitration signal connected to a reset input of the set-reset latch and a true output of the set-reset latch connected to the inhibit input of the first logic means.