Patent US5136189A successfully refreshed from Google Patents.
US5136189A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bicmos input circuit for detecting signals out of ecl range
Assignee: National Semiconductor Corp
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Filing: 1990-04-02
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Granted: 1992-08-04
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Expires: 2010-04-02
Abstract
Abstract A BiCMOS input circuit which is capable of detecting signals below a particular range, such as ECL signals, is presented. The circuit is useful in conserving the number of pins in a BiCMOS integrated circuit in that a signal below normal ECL levels can trigger special functions, such as testing. The circuit has a plurality of CMOS inverter circuits connected in series with the input node of the first inverter connected to the input terminal of the circuit and the output node of the last inverter circuit connected to the output terminal of the circuit. Diode-connected bipolar transistor created a potential difference between V CC and the source electrode of PMOS transistor of each CMOS inverter circuit in a declining fashion from the first inverter to the last inverter. The last inverter circuit has no potential difference at all so that its output has a full CMOS swing.
Inventors
- 👤 James E. Demaris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:13
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; H03K19/1732; H03K19/0175
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
329 words
An input circuit for a BiCMOS integrated circuit, said integrated circuit capable of receiving signals in a predetermined range of logic levels through an input terminal, said input circuit connected to said input terminal, comprising a first signal path connecting said input terminal to a circuit responsive to signals in said predetermined range of logic level; a second signal path having a plurality of CMOS inverter circuits, each inverter circuit having a first power supply node coupled to a first voltage reference, a second power supply node coupled to a second voltage reference, an input node and an output node, said inverter circuits coupled serially to each other from first to last, an output node of one inverter circuit connected to the input node of the following inverter circuit, an input node of said first inverter circuit connected to said input terminal, an output node of said last inverter circuit connected to an output terminal; and potential difference means connected at least between said first power supply node of said first inverter circuit and said first voltage reference, said plurality of CMOS inverter circuits include one or more inverter circuits between said first and last inverter circuits, said potential difference means generating potential differences between said first power supply node of said inverter circuits and said first voltage reference, the potential difference decreasing from said first inverter circuit to said last inverter circuit, said last inverter circuit having no potential difference between said first power supply terminal of said last inverter circuit and said first voltage reference so that said inverters switch states at a signal having a voltage level below said predetermined range of logic level; whereby said BiCMOS integrated circuit receives signals in said predetermined range of logic level on said first signal path from said input terminal and receives signals on said second signal path from said input terminal to said output terminal only if said signals are below said predetermined range of logic level signals.
Claim 2
Dependent Claim
329 words
An input circuit for a BiCMOS integrated circuit, said integrated circuit capable of receiving signals in a predetermined range of logic levels through an input terminal, said input circuit connected to said input terminal, comprising a first signal path connecting said input terminal to a circuit responsive to signals in said predetermined range of logic level; a second signal path having a plurality of CMOS inverter circuits, each inverter circuit having a first power supply node coupled to a first voltage reference, a second power supply node coupled to a second voltage reference, an input node and an output node, said inverter circuits coupled serially to each other from first to last, an output node of one inverter circuit connected to the input node of the following inverter circuit, an input node of said first inverter circuit connected to said input terminal, an output node of said last inverter circuit connected to an output terminal; and potential difference means connected at least between said first power supply node of said first inverter circuit and said first voltage reference, said plurality of CMOS inverter circuits include one or more inverter circuits between said first and last inverter circuits, said potential difference means generating potential differences between said first power supply node of said inverter circuits and said first voltage reference, the potential difference decreasing from said first inverter circuit to said last inverter circuit, said last inverter circuit having no potential difference between said first power supply terminal of said last inverter circuit and said first voltage reference so that said inverters switch states at a signal having a voltage level below said predetermined range of logic level; whereby said BiCMOS integrated circuit receives signals in said predetermined range of logic level on said first signal path from said input terminal and receives signals on said second signal path from said input terminal to said output terminal only if said signals are below said predetermined range of logic level signals.
Claim 3
Dependent Claim
41 words
The input circuit for a BiCMOS integrated circuit as in claim 1 wherein said potential difference means comprises at least one diode-connected bipolar transistor connected in series between said power supply node of said inverter circuits and said first voltage reference.
Claim 4
Dependent Claim
20 words
The input circuit for a BiCMOS integrated circuit as in claim 2 wherein said predetermined range comprises ECL voltage levels.
Claim 5
Dependent Claim
31 words
The input circuit for a BiCMOS integrated circuit as in claim 2 further comprising a current source connected to said bipolar transistor for maintaining said bipolar transistor in a on state.
Claim 6
Dependent Claim
21 words
The input circuit for a BiCMOS integrated circuit as in claim 4 wherein said current source comprises a diode-connected MOS transistor.
Claim 7
Dependent Claim
134 words
The input circuit for a BiCMOS integrated circuit as in claim 1 wherein said each of said CMOS inverter circuits comprises a PMOS transistor and an NMOS transistor, each transistor having a source electrode, drain electrode and gate electrode, said drain electrodes of both transistors in common forming said output node, said gate electrodes of both transistors in common forming said input node, said source electrode of said NMOS transistor forming said second voltage supply node, said source electrode of said PMOS transistor forming said first voltage supply node, said substrate of said PMOS transistor held at the same voltage as said PMOS transistor source electrode, whereby said PMOS transistor turns on when the voltage at said input node is lower than the sum of said source electrode voltage and PMOS transistor threshold voltage.
Claim 8
Dependent Claim
38 words
The input circuit for a BiCMOS integrated circuit as in claim 6 wherein said potential difference means is such that said PMOS transistor of said first inverter circuit turns on when said input signal is below ECL levels.
Claim 9
Dependent Claim
32 words
The input circuit for a BiCMOS integrated circuit as in claim 7 wherein the amount of said potential difference is two V BE , the forward base-emitter drop of a bipolar transistor.
Claim 10
Dependent Claim
207 words
A BiCMOS circuit having an input terminal and an output terminal, said circuit capable of detecting signals on said input terminal below ECL voltage ranges, said BiCMOS circuit comprising a first, second and third CMOS inverter circuits, each having a first power supply node coupled to a first voltage reference, a second power supply node coupled to a second voltage reference, an input node and an output node, said first inverter circuit input node connected to said input terminal, said first inverter output node connected to said second inverter input node, said second inverter output node connected to said third inverter input node, and said third inverter output node connected to said output terminal; a first bipolar potential difference means connected between said first power supply node of said first inverter and said first voltage reference; and a second bipolar potential difference means connected between said first power supply node of said second inverter and said first voltage reference, the amount of potential difference of said second bipolar potential difference means being less than that of said first bipolar potential difference means; whereby said BiCMOS circuit transmits a signal on said input terminal to said output terminal when said signal is below an ECL range of values.
Claim 11
Dependent Claim
207 words
A BiCMOS circuit having an input terminal and an output terminal, said circuit capable of detecting signals on said input terminal below ECL voltage ranges, said BiCMOS circuit comprising a first, second and third CMOS inverter circuits, each having a first power supply node coupled to a first voltage reference, a second power supply node coupled to a second voltage reference, an input node and an output node, said first inverter circuit input node connected to said input terminal, said first inverter output node connected to said second inverter input node, said second inverter output node connected to said third inverter input node, and said third inverter output node connected to said output terminal; a first bipolar potential difference means connected between said first power supply node of said first inverter and said first voltage reference; and a second bipolar potential difference means connected between said first power supply node of said second inverter and said first voltage reference, the amount of potential difference of said second bipolar potential difference means being less than that of said first bipolar potential difference means; whereby said BiCMOS circuit transmits a signal on said input terminal to said output terminal when said signal is below an ECL range of values.
Claim 12
Dependent Claim
23 words
The BiCMOS circuit as in claim 9 wherein said first and second bipolar potential difference means comprises at least one diode-connected bipolar transistor.
Claim 13
Dependent Claim
33 words
The BiCMOS circuit as in claim 10 wherein said first bipolar potential difference means comprises two diode-connected bipolar transistor in series and said second bipolar potential difference means comprises one diode-connected bipolar transistor.
Claim 14
Dependent Claim
34 words
The BiCMOS circuit as in claim 11 further comprising first and second current sources connected to said first and second bipolar potential difference means for maintaining said diode-connected bipolar transistors in an on state.
Claim 15
Dependent Claim
17 words
The BiCMOS circuit as in claim 12 wherein said first and second current sources comprise MOS transistors.
Claim 16
Dependent Claim
120 words
The BiCMOS circuit as in claim 10 wherein said first bipolar potential difference means comprises first and second NPN transistors, each having common base/collector electrodes tied together and an emitter electrode, said first transistor base/collector electrode connected to said first voltage reference, said first transistor emitter electrode connected to said second transistor base/collector electrode, said second transistor emitter electrode connected to said first power supply node of said first inverter; said second bipolar potential difference means comprises a third NPN transistor having a common base/collector electrode tied together and an emitter electrode, said third transistor base/collector electrode connected to said first voltage reference, said third transistor emitter electrode connected to said first power supply node of said second inverter circuit.
Claim 17
Dependent Claim
87 words
The BiCMOS circuit as in claim 14 further comprising said first current source having a first MOS transistor with a common gate/drain electrode and a source electrode, said gate/drain electrode connected to said emitter electrode of said second bipolar transistor; and said second current source having a second MOS transistor with a gate electrode, a drain electrode and a source electrode, said drain electrode connected to said emitter electrode of said third transistor and said gate electrode connected to said emitter electrode of said second bipolar transistor.
Claim 18
Dependent Claim
26 words
The BiCMOS circuit as in claim 15 wherein said gate electrode of said second MOS transistor is connected to said emitter electrode of said second transistor.
Claim 19
Dependent Claim
129 words
The BiCMOS circuit as in claim 9 wherein said each of said CMOS inverter circuits comprises a PMOS transistor and an NMOS transistor, each transistor having a source electrode, drain electrode and gate electrode, said drain electrodes of both transistors in common forming said output node, said gate electrodes of both transistors in common forming said input node, said source electrode of said NMOS transistor forming said second voltage supply node, said source electrode of said PMOS transistor forming said first voltage supply node, said substrate of said PMOS transistor held at the same voltage as said PMOS transistor source electrode, whereby said PMOS transistor turns on when the voltage at said input node is lower than the sum of said source electrode voltage and PMOS transistor threshold voltage.
Claim 20
Dependent Claim
24 words
The BiCMOS circuit as in claim 9 further comprising a signal path connecting said input terminal to a circuit responsive to ECL level signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-04 | 1996-02-03 | 1996-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-04 | 2000-02-03 | 2000-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-04 | 2004-02-03 | 2004-08-04 | $7700.00 | Window Closed / Lapsed |