Patent US5132569A successfully refreshed from Google Patents.
US5132569A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed Bi-COMS input circuit fabricated from a small number of circuit components
Assignee: NEC Corp
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Filing: 1990-11-15
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Granted: 1992-07-21
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Expires: 2010-11-15
Abstract
Abstract An input circuit is responsive to a TTL-level input signal for producing a CMOS-level output signal and the complementary signal thereof and comprises a first inverter circuit implemented by a series combination of a p-channel type field effect transistor, a first output node and an n-p-n type bipolar transistor and responsive to the TTL-level input signal and a control signal opposite in phase to the input signal for producing the CMOS-level complementary output signal, a second inverter circuit implemented by a series combination of n-channel type field effect transistors and responsive to the input signal for producing the control signal, and a third inverter circuit implemented by a series combination of a p-channel type field effect transistor and an n-channel type field effect transistor and responsive to the CMOS-level complementary output signal for producing the CMOS-level output signal at a second output node, wherein the p-channel type field effect transistor of the first inverter circuit is enlarged without increasing the size of the bipolar transistor because a bipolar transistor is much larger in current driving capability than a field transistor, thereby achieving a high-speed operation.
Inventors
- 👤 Zensuke Matsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
421 words
An input circuit responsive to an input signal for producing an output signal and a complementary output signal, said input signal swinging its voltage level in a first voltage range, said output signal and said complementary output signal swinging their voltage levels in a second voltage range different from said first voltage range, said input circuit comprising: a) a first inverter circuit coupled between first and second sources of voltage level different in voltage level and implemented by a series combination of a field effect transistor, a first output node and a bipolar transistor, said field effect transistor and said bipolar transistor being responsive to said input signal at an input node and a control signal for producing said complementary output signal at said first output node through complementary switching actions, b) a second inverter circuit coupled between said first output node and said second source of voltage level and implemented by a series combination of field effect transistors, said field effect transistors of said second inverter circuit being responsive to said input signal and said complementary output signal for producing said control signal at a control node between said field effect transistors of said second inverter circuit, and c) a third inverter circuit coupled between said first and second sources of voltage level and implemented by a series combination of field effect transistors, said field effect transistors of said third inverter circuit being responsive to said complementary output signal for producing said output signal at a second output node, said field effect transistor of said first inverter circuit having a first channel conductivity type, said second inverter circuit comprising a series combination of two field effect transistors with a second channel conductivity type opposite to said first channel conductivity type, said two field effect transistors having respectively gate electrode coupled to said input node and said first output node, respectively, said third inverter circuit comprising a series combination of a field effect transistor of said first channel conductivity type and a field effect transistor of said second channel conductivity type gate electrodes of which are coupled to said first output node, said input circuit further comprising a first gate transistor of said first channel conductivity type coupled between said field effect transistor of said first inverter circuit and said first source of voltage level, and a second gate transistor coupled between said first output node and the base node of said bipolar transistor, said first and second gate transistors being responsive to an enable signal for activating said input circuit.
Claim 2
Dependent Claim
421 words
An input circuit responsive to an input signal for producing an output signal and a complementary output signal, said input signal swinging its voltage level in a first voltage range, said output signal and said complementary output signal swinging their voltage levels in a second voltage range different from said first voltage range, said input circuit comprising: a) a first inverter circuit coupled between first and second sources of voltage level different in voltage level and implemented by a series combination of a field effect transistor, a first output node and a bipolar transistor, said field effect transistor and said bipolar transistor being responsive to said input signal at an input node and a control signal for producing said complementary output signal at said first output node through complementary switching actions, b) a second inverter circuit coupled between said first output node and said second source of voltage level and implemented by a series combination of field effect transistors, said field effect transistors of said second inverter circuit being responsive to said input signal and said complementary output signal for producing said control signal at a control node between said field effect transistors of said second inverter circuit, and c) a third inverter circuit coupled between said first and second sources of voltage level and implemented by a series combination of field effect transistors, said field effect transistors of said third inverter circuit being responsive to said complementary output signal for producing said output signal at a second output node, said field effect transistor of said first inverter circuit having a first channel conductivity type, said second inverter circuit comprising a series combination of two field effect transistors with a second channel conductivity type opposite to said first channel conductivity type, said two field effect transistors having respectively gate electrode coupled to said input node and said first output node, respectively, said third inverter circuit comprising a series combination of a field effect transistor of said first channel conductivity type and a field effect transistor of said second channel conductivity type gate electrodes of which are coupled to said first output node, said input circuit further comprising a first gate transistor of said first channel conductivity type coupled between said field effect transistor of said first inverter circuit and said first source of voltage level, and a second gate transistor coupled between said first output node and the base node of said bipolar transistor, said first and second gate transistors being responsive to an enable signal for activating said input circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |