US5132235A
Expired / Lapsed
US
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Method for fabricating a high voltage MOS transistor
Assignee: Vishay Siliconix Inc
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Filing: 1991-03-29
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Granted: 1992-07-21
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Expires: 2011-03-29
Abstract
Abstract A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer. Using this method, the high concentration of slow diffusing N type antimony or arsenic dopant in the buried layer will not out-diffuse into the N-well region and adversely affect the breakdown voltage between the source or drain and the N-well. The out-diffusing of the phosphorus into the epitaxial layer, however, will merge with the phosphorus diffusion from the top to form a uniform N type concentration in the N-well.
Inventors
- 👤 Richard K. Williams
- 👤 Robert W. Busse
- 👤 Richard A. Blanchard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/421; H10D30/028; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10W; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/085
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
228 words
A method for forming an MOS transistor with reduced parasitic transistor current gain, comprising the steps of: introducing a first dopant of a first conductivity type into a first region of a substrate of a second conductivity type, said first dopant being a slow diffusing type; introducing a second dopant of a first conductivity type into said first region, said second dopant being a fast diffusing type; growing an epitaxial layer of a second conductivity type at least over said first region, said epitaxial layer having an upper surface; introducing said second dopant of a first conductivity type into said upper surface of said epitaxial layer over said first region to form an upper well region, said dopant from said upper well region diffusing and merging together with said second dopant introduced into said first region of said substrate to form a continuous well region, said first dopant, being of a slow diffusing type, diffusing a relatively small distance into said epitaxial layer and forming a buried layer; introducing a third dopant of a second conductivity type into second and third regions within said upper well region, said second and third regions forming a source region and drain region, respectively; forming a gate oxide layer over said upper well region between said source region and said drain region; and forming a control gate over said gate oxide layer.
Claim 2
Independent Claim
228 words
A method for forming an MOS transistor with reduced parasitic transistor current gain, comprising the steps of: introducing a first dopant of a first conductivity type into a first region of a substrate of a second conductivity type, said first dopant being a slow diffusing type; introducing a second dopant of a first conductivity type into said first region, said second dopant being a fast diffusing type; growing an epitaxial layer of a second conductivity type at least over said first region, said epitaxial layer having an upper surface; introducing said second dopant of a first conductivity type into said upper surface of said epitaxial layer over said first region to form an upper well region, said dopant from said upper well region diffusing and merging together with said second dopant introduced into said first region of said substrate to form a continuous well region, said first dopant, being of a slow diffusing type, diffusing a relatively small distance into said epitaxial layer and forming a buried layer; introducing a third dopant of a second conductivity type into second and third regions within said upper well region, said second and third regions forming a source region and drain region, respectively; forming a gate oxide layer over said upper well region between said source region and said drain region; and forming a control gate over said gate oxide layer.
Claim 3
Dependent Claim
69 words
The method of claim 1 wherein both of said steps of introducing a second dopant are further characterized in that said concentration of dopants in said first region of said substrate and said upper well region diffuse so as not to adversely affect the breakdown voltage of the device as compared to the breakdown voltage of the device without said second dopant introduced into said region of said substrate.
Claim 4
Dependent Claim
25 words
The method of claim 2 wherein said first dopant is selected from the group consisting of antimony and arsenic and said second dopant is phosphorus.
Claim 5
Dependent Claim
35 words
The method of claim 2 further comprising the step of introducing said third dopant of a second conductivity type into a fourth region to form a lightly doped drain extension contiguous with said drain region.
Claim 6
Dependent Claim
31 words
The method of claim 2 further comprising the step of introducing a dopant of first conductivity type into a region of said upper well region to form a well contact region.
Claim 7
Dependent Claim
17 words
The method of claim 2 wherein said first dopant is boron and said second dopant is aluminum.
References Cited (Backward Citations)
US3702428A
Cited
US3547716A
Cited
US3723199A
Cited
US3802968A
Cited
US4032372A
Cited
US3993512A
Cited
US3865648A
Cited
US3929526A
Cited
JPS553806A
Cited
US4311532A
Cited
US4404048A
Cited
US4529456A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |