Patent US5128970A successfully refreshed from Google Patents.
US5128970A
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US
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Non-return to zero synchronizer
Assignee: Unisys Corp
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Filing: 1990-12-20
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Granted: 1992-07-07
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Expires: 2010-12-20
Abstract
Abstract A non-return-to-zero synchronizer is described which creates an output pulse signal that is synchronized to a system clock signal, from an asynchronous input strobe signal which can occur at any point in a given system clock cycle. The first circuit element within the synchronizer captures the input strobe and toggles the state of its data output terminal in response to successive pulses of the asynchronous input strobe signal. The remaining portion of the synchronizer responds to each change in the state of the first circuit element and to produce an output pulse having a duration of one clock cycle. An alternative embodiment is described which utilizes a sequential logic circuit to generate the desired output pulse. Because the synchronizer uses a state change to indicate the occurrence of a strobe, the problem of resetting the initial circuit element to a particular logic level is eliminated.
Inventors
- 👤 Philip A. Murphy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:40
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
122 words
Apparatus, for use in synchronizing an asynchronous input signal to a periodic clock signal, comprising: a first latching element for detecting and capturing the asynchronous input signal, wherein said latching element is not reset to a fixed, initial state between occurrences of the asynchronous input signal and said latching element exhibits a change of state independent of said clock signal; a second latching element for synchronizing the output signal of said first latching element with the clock signal; gating means responsive to the output signal of the second latching element and to said clock signal for generating an output pulse signal having a duration not greater than one period of said clock signal from the output signal of said second latching element.
Claim 2
Dependent Claim
122 words
Apparatus, for use in synchronizing an asynchronous input signal to a periodic clock signal, comprising: a first latching element for detecting and capturing the asynchronous input signal, wherein said latching element is not reset to a fixed, initial state between occurrences of the asynchronous input signal and said latching element exhibits a change of state independent of said clock signal; a second latching element for synchronizing the output signal of said first latching element with the clock signal; gating means responsive to the output signal of the second latching element and to said clock signal for generating an output pulse signal having a duration not greater than one period of said clock signal from the output signal of said second latching element.
Claim 3
Dependent Claim
31 words
The apparatus set forth in claim 1, wherein: said asynchronous input signal is a pulse signal which occurs less than once during any two successive cycles of said periodic clock signal.
Claim 4
Dependent Claim
161 words
Apparatus, for use in synchronizing an asynchronous input signal to a known, a system clock signal, comprising: first latching means, having an internal state and being responsive to a predetermined transition of said asynchronous input signal for changing said internal state between first and second values and for providing said internal state as an output signal; and second latching means, coupled to receive said clock signal and having first and second data output terminals which provide respective normal and inverted signals for aligning the signal provided by said first latching means with the system clock signal; means, including multiple-input latching means, coupled to receive said clock signal and having at least first and second data input terminals coupled to the respective first and second data output terminals of said second latching means, for producing an active high output pulse one clock cycle in duration responsive to at least one of the normal and inverted signals provided by said second latching means.
Claim 5
Dependent Claim
161 words
Apparatus, for use in synchronizing an asynchronous input signal to a known, a system clock signal, comprising: first latching means, having an internal state and being responsive to a predetermined transition of said asynchronous input signal for changing said internal state between first and second values and for providing said internal state as an output signal; and second latching means, coupled to receive said clock signal and having first and second data output terminals which provide respective normal and inverted signals for aligning the signal provided by said first latching means with the system clock signal; means, including multiple-input latching means, coupled to receive said clock signal and having at least first and second data input terminals coupled to the respective first and second data output terminals of said second latching means, for producing an active high output pulse one clock cycle in duration responsive to at least one of the normal and inverted signals provided by said second latching means.
Claim 6
Dependent Claim
80 words
The apparatus set forth in claim 3, wherein the means for producing said active high output pulse further comprises: a latching circuit means coupled to receive the active high output pulse and the system clock signal; and enabling circuitry means, coupled to the second latching means, for alternately enabling the multiple-input latching means to be responsive to one of the normal and inverted signals which are provided to the respective first and second input terminals of the multiple-input latching means.
Claim 7
Dependent Claim
33 words
The apparatus set forth in claim 3, wherein the second latching means is of a type having a relatively high metastability immunity and is placed in close proximity to the multiple-input latching means.
Claim 8
Independent Claim
91 words
A method for synchronizing an asynchronous input strobe signal to a periodic clock signal, comprising the steps of: asynchronously capturing said input strobe signal using a first latching circuit element; converting said captured input strobe signal to a change of state of an output signal of said first latching circuit element; aligning the output signal of the first latching circuit element with the clock signal; and generating an output pulse signal in synchronism with said aligned signal, said output pulse signal having pulses that are approximately one clock cycle in duration.
Claim 9
Independent Claim
91 words
A method for synchronizing an asynchronous input strobe signal to a periodic clock signal, comprising the steps of: asynchronously capturing said input strobe signal using a first latching circuit element; converting said captured input strobe signal to a change of state of an output signal of said first latching circuit element; aligning the output signal of the first latching circuit element with the clock signal; and generating an output pulse signal in synchronism with said aligned signal, said output pulse signal having pulses that are approximately one clock cycle in duration.
Claim 10
Dependent Claim
103 words
Apparatus for synchronizing an asynchronous input strobe signal to a system clock signal, comprising: capture means, having first and second states, asynchronously responsive to said input strobe signal for translating said input strobe signal to a transition between the first and second states; synchronizing means, coupled to the capture means, for translating the change in state by said capture means into a change in state synchronized to said system clock signal; and means responsive to said synchronized state change for generating a pulse signal having a transition which has a substantially fixed delay with respect to a transition of said system clock signal.
Claim 11
Dependent Claim
103 words
Apparatus for synchronizing an asynchronous input strobe signal to a system clock signal, comprising: capture means, having first and second states, asynchronously responsive to said input strobe signal for translating said input strobe signal to a transition between the first and second states; synchronizing means, coupled to the capture means, for translating the change in state by said capture means into a change in state synchronized to said system clock signal; and means responsive to said synchronized state change for generating a pulse signal having a transition which has a substantially fixed delay with respect to a transition of said system clock signal.
Claim 12
Dependent Claim
94 words
Apparatus, for use in synchronizing an asynchronous input signal to a periodic clock signal, comprising: a first latching element for producing a state-change signal which changes between first and second states in synchronism with said asynchronous input signal; a second latching element, responsive to said clock signal, for synchronizing the state-change signal with the clock signal; a sequential logic circuit coupled to said second latching element and responsive to said clock signal for generating an output pulse signal for each change of state of the synchronized output signal provided by said second latching element.
Claim 13
Dependent Claim
94 words
Apparatus, for use in synchronizing an asynchronous input signal to a periodic clock signal, comprising: a first latching element for producing a state-change signal which changes between first and second states in synchronism with said asynchronous input signal; a second latching element, responsive to said clock signal, for synchronizing the state-change signal with the clock signal; a sequential logic circuit coupled to said second latching element and responsive to said clock signal for generating an output pulse signal for each change of state of the synchronized output signal provided by said second latching element.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |