US4926445A
Expired / Lapsed
US
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External asynchronous input tester for bit slice machines
Assignee: United States Department of the Air Force
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Filing: 1987-07-01
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Granted: 1990-05-15
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Expires: 2007-07-01
Abstract
Abstract A timing circuit is disclosed for use with microprocessors which perform bit slicing within their arithmetic logic units. This timing circuit combines the synchronization of digital data inputs with the generation of the clocking signal, by dividing an oscillator frequency signal into the clocking signal, using a number of cycles of the oscillator frequency signal to synchronize the digital data inputs with the clocking signal, and outputting a synchronized clocking signal as soon as the digital data input signals are synchronized with the clocking signals. In a situation where the clock is derived by dividing the oscillator frequency by four, two of the four oscillator cycles are used to resynchronize the test input. The waste of overhead wait states and individual input resynchronization circuits are eliminated.
Inventors
- 👤 James R. Robb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:43
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
330 words
A timing circuit which produces a clicking signal for a microprocessor which is resynchronized with digital data input signals, said clocking signal having a value and said timing circuit comprising: an oscillator which produces an oscillator frequency signal which has a value; a digital multiplexer which receives and inverts said digital data input signals to produce output signals; an AND gate which has a first and second input terminal and an output terminal, said AND gate receiving said output signals from said digital multiplexer on its first input terminal, said AND gate receiving an anti-clocking signal over its second input terminal, said anti-clocking signal being an inverse signal with respect to said clocking signal, said AND gate producing an output signal over its output terminal by performing an AND function using said output signals from said digital multiplexer and said anti-clocking signal; a first flip flop which has a data input terminal, a clock input terminal, and a 1 side output terminal, said first flip flop receiving the output signal from said AND gate over its data input terminal, said first flip flop receiving said oscillator frequency signal from said oscillator over its clock input terminal, said first flip flop producing an output signal over its 1 side output terminal; and a second flip flop which outputs said clocking signal and said anti-clocking signal such that the value of said clocking signal is produced by dividing the value of said oscillator frequency signal by four and synchronizes said microprocessor with said digital data input signals, said second flip flop receiving the output signal of said first flip flop over a data input terminal of said second flip flop, said second flip flop having a clock input terminal which receives said oscillator frequency signal from said oscillator, said second flip flop having a 1 side output terminal over which it outputs said clocking signal, said second flip flop having an 0 side output terminal over which it outputs said anti-clocking signal.
Claim 2
Dependent Claim
330 words
A timing circuit which produces a clicking signal for a microprocessor which is resynchronized with digital data input signals, said clocking signal having a value and said timing circuit comprising: an oscillator which produces an oscillator frequency signal which has a value; a digital multiplexer which receives and inverts said digital data input signals to produce output signals; an AND gate which has a first and second input terminal and an output terminal, said AND gate receiving said output signals from said digital multiplexer on its first input terminal, said AND gate receiving an anti-clocking signal over its second input terminal, said anti-clocking signal being an inverse signal with respect to said clocking signal, said AND gate producing an output signal over its output terminal by performing an AND function using said output signals from said digital multiplexer and said anti-clocking signal; a first flip flop which has a data input terminal, a clock input terminal, and a 1 side output terminal, said first flip flop receiving the output signal from said AND gate over its data input terminal, said first flip flop receiving said oscillator frequency signal from said oscillator over its clock input terminal, said first flip flop producing an output signal over its 1 side output terminal; and a second flip flop which outputs said clocking signal and said anti-clocking signal such that the value of said clocking signal is produced by dividing the value of said oscillator frequency signal by four and synchronizes said microprocessor with said digital data input signals, said second flip flop receiving the output signal of said first flip flop over a data input terminal of said second flip flop, said second flip flop having a clock input terminal which receives said oscillator frequency signal from said oscillator, said second flip flop having a 1 side output terminal over which it outputs said clocking signal, said second flip flop having an 0 side output terminal over which it outputs said anti-clocking signal.
Claim 3
Dependent Claim
181 words
A timing circuit, as defined in claim 1, wherein said dividing means includes a divide-by-three timing circuit which comprises: a first flip-flop which has a data input terminal, a clear input terminal, a clock input terminal, and a 1-side output terminal, said first flip-flop receiving said output signals from said digital multiplexer over its data input terminal, said first flip-flop receiving said oscillator frequency signal, from said oscillator, over its clock input terminal, said first flip-flop receiving and inverting an anti-clocking signal over its clear input terminal where said anti-clocking signal is an inverse signal with respect to said clocking signal, said first flip-flop producing an output signal therefrom over its 1-side output terminal; and a second flip-flop which has a data input terminal over which it receives the output of said first flip-flop, said second flip-flop having a clock input terminal over which it receives said oscillator frequency signal from said oscillator, said second flip-flop having a 1- side output terminal over which it outputs said clocking signal, and an O-side output terminal over which it outputs said anti-clocking terminal.
Claim 4
Dependent Claim
224 words
A timing circuit, as defined in claim 1, wherein said dividing means includes a divide-by-four timing circuit which comprises: a first flip-flop which has a data input terminal over which it receives said output signals from said digital multiplexer, said first flip-flop having a clock input terminal over which it receives said oscillator frequency signal from said oscillator, said first flip-flop having a clear terminal over which it receives a NAND output signal, said first flip-flop having a 1- side output over which it produces an output signal; a second flip-flop having a data input terminal over which it receives the output signal of the first flip-flop, said second flip-flop having a clock input terminal over which it receives said oscillator frequency signal from said oscillator, said second flip-flop having a 1-side output terminal over which it produces an output signal; a third flip-flop which has a data input terminal over which it receives the output signal of said second flip-flop, said third flip-flop having a clock input terminal over which it receives the clocking frequency signal from said oscillator, said third flip-flop having a 1-side output terminal over which it outputs said clocking signal; and a NAND gate which produces said NAND output signal from the output signal of said second flip-flop, and from the clocking signal it receives from said third flip-flop.
Claim 5
Dependent Claim
47 words
A timing circuit, as defined in claim 3, including a single step test circuit which inputs a controllable wait into the digital multiplexer to stop the clock signal, said single step test circuit capable of inputting a signal into the digital multiplexer to restart the clock signal.
Claim 6
Dependent Claim
18 words
A timing circuit, as defined in claim 3, including a halt test circuit which inputs the clock signal.
Claim 7
Dependent Claim
98 words
A process of producing a clocking signal which has a value to synchronize a microprocessor with digital data input signals, said process comprising the steps of: generating an oscillator frequency signal which has a value; performing a divide-by-four on said oscillator frequency signal to produce said clocking signal composed of four cycles of said oscillator frequency signal; using two of said four cycles of said oscillator frequency signal to synchronize said digital data input signals with said clocking signal; and outputting said clocking signal as soon as said digital data input signals are synchronized with said clocking signal.
Claim 8
Dependent Claim
98 words
A process of producing a clocking signal which has a value to synchronize a microprocessor with digital data input signals, said process comprising the steps of: generating an oscillator frequency signal which has a value; performing a divide-by-four on said oscillator frequency signal to produce said clocking signal composed of four cycles of said oscillator frequency signal; using two of said four cycles of said oscillator frequency signal to synchronize said digital data input signals with said clocking signal; and outputting said clocking signal as soon as said digital data input signals are synchronized with said clocking signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |