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US5128731A
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Static random access memory cell using a P/N-MOS transistors
Assignee: Renesas Electronics America Inc
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Filing: 1990-06-13
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Granted: 1992-07-07
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Expires: 2010-06-13
Abstract
Abstract A P/N-MOS transistor having source and drain of opposite semiconductor types is provided. One embodiment of the P/N-MOS transistor has turn-off characteristic similar to a PMOS transistor, and turn-on characteristic similar to a PMOS transistor connected in series with a p-n junction diode. An application of the P/N-MOS transistor is provided in a static random access memory (SRAM) cell. This SRAM cell has density advantage over SRAM cells using polysilicon PMOS transistors as active transistors.
Inventors
- 👤 Chuen-Der Lien
- 👤 Fu-Chieh Hsu
- 👤 Jeong Y. Choi
- 👤 Jeng-Jiun Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:32
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
120 words
A static random access memory cell comprising: first and second polysilicon P/N-MOS transistors, each having a gate, a source region, and a drain region being of a different conductivity as said source region; first and second NMOS transistors, each having a gate, a source region and a drain region, wherein said drain region of said first P/N-MOS transistor, said gate of said second NMOS transistor, and said gate of said second P/N-MOS transistor are connected to said drain region of said first NMOS transistor and wherein said drain region of said second P/N-MOS transistor, said gate of said first NMOS transistor, and said gate of said first P/N-MOS transistor are connected to said drain region of said second NMOS transistor.
Claim 2
Dependent Claim
120 words
A static random access memory cell comprising: first and second polysilicon P/N-MOS transistors, each having a gate, a source region, and a drain region being of a different conductivity as said source region; first and second NMOS transistors, each having a gate, a source region and a drain region, wherein said drain region of said first P/N-MOS transistor, said gate of said second NMOS transistor, and said gate of said second P/N-MOS transistor are connected to said drain region of said first NMOS transistor and wherein said drain region of said second P/N-MOS transistor, said gate of said first NMOS transistor, and said gate of said first P/N-MOS transistor are connected to said drain region of said second NMOS transistor.
Claim 3
Dependent Claim
76 words
A static random access memory cell as in claim 1, further comprising: first and second transfer gates each having input and output leads, said output lead of said first transfer gate connected to said drain of said first polysilicon P/N-MOS transistor and said drain of said first NMOS transistor, and said output lead of said second transfer gate connected to said drain of said second polysilicon P/N-MOS transistor and said drain of said second NMOS transistor.
Claim 4
Dependent Claim
129 words
A static random access memory cell as in claim 1 wherein said polysilicon P/N-MOS transistor comprises: a control region being said gate of said P/N-MOS transistor for application of a control voltage; a channel region separated from said control region by an insulating material, said channel region conducting a current when said control voltage is applied and not conducting a current when said control voltage is not applied; a first region being of a first conductivity type and adjacent said channel region, said first region having a lead for application of a first bias voltage; and a second region being of a second conductivity type and adjacent said channel region but separated from said first region, said second region having a lead for application of a second bias voltage.
Claim 5
Dependent Claim
32 words
A static random access memory cell as in claim 3, wherein said first conductivity type is that of a p-type semiconductor and said second conductivity type is that of a n-type semiconductor.
Claim 6
Dependent Claim
19 words
A static random access memory cell as in claim 3, wherein said channel region comprises lightly doped n-type semiconductor.
Claim 7
Dependent Claim
19 words
A static random access memory cell as in claim 3, wherein said channel region comprises lightly doped p-type semiconductor.
Claim 8
Dependent Claim
31 words
A static random access memory cell as in claim 1, wherein said gate of said first NMOS transistor and said gate of said first P/N-MOS transistor share a common gate structure.
Claim 9
Dependent Claim
31 words
A static random access memory cell as in claim 1, wherein said gate of said second NMOS transistor and said gate of said second P/N-MOS transistor share a common gate structure.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |