Patent US5128279A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5128279A Expired / Lapsed US ⏱️ 0.0 years remaining

Charge neutralization using silicon-enriched oxide layer

Assignee: NXP BV
•
Filing: 1991-10-11
•
Granted: 1992-07-07
•
Expires: 2011-10-11
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.

Inventors

  • 👤 Subhash R. Nariani
  • 👤 Dipankar Pramanik

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 17:58
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10W74/43; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10B; H10B69/00; Y; Y10; Y10S; Y10S438/00; Y10S438/958

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 67 words
In the manufacture of an integrated circuit structure including a substrate, an intermetal dielectric having an organic glass layer and a passivation structure including a nitride layer, a method of limiting charge in the resulting integrated circuit structure, said method comprising: forming a silicon-enriched oxide intermetal dielectric layer over a first-level metallization and said substrate; and forming said organic glass layer directly over said silicon-enriched oxide layer.
Claim 2
Dependent Claim 67 words
In the manufacture of an integrated circuit structure including a substrate, an intermetal dielectric having an organic glass layer and a passivation structure including a nitride layer, a method of limiting charge in the resulting integrated circuit structure, said method comprising: forming a silicon-enriched oxide intermetal dielectric layer over a first-level metallization and said substrate; and forming said organic glass layer directly over said silicon-enriched oxide layer.
Claim 3
Dependent Claim 26 words
A method as recited in claim 1 wherein said silicon-enriched oxide layer contains a spin density of at least about 10 17 per cm 3 .
Claim 4
Dependent Claim 19 words
The method of claim 1 further comprising forming an additional silicon-enriched oxide dielectric layer over said organic glass layer.
Claim 5
Dependent Claim 30 words
The method of claim 1 further comprising forming a silicon-enriched oxide passivation layer over a second-level metallization and then forming said nitride passivation layer on said silicon-enriched oxide passivation layer.
Claim 6
Dependent Claim 39 words
The method of claim 1 wherein said silicon-enriched oxide intermetal dielectric layer is formed using a plasma deposition in which a silicon-bearing reactant is presented in amount relative to oxygen-bearing reactant above that required for stochiometric silicon dioxide formation.

References Cited (Backward Citations)

US4123565A Cited
US4381595A Cited
US4502202A Cited
US4613888A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-07-07 1996-01-06 1996-07-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-07-07 2000-01-06 2000-07-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-07-07 2004-01-06 2004-07-07 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag