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Method of resetting sequence of access to extended memory disrupted by interrupt processing in 80286 compatible system using code segment register
Assignee: Microsoft Technology Licensing LLC
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Filing: 1988-11-07
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Granted: 1992-06-23
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Expires: 2008-11-07
Abstract
Abstract A method and system for allowing an interrupted computer program to detect the occurrence of an interrupt. In a preferred embodiment, a system according to the present invention allows an Intel 80286-compatible based computer program executing in real mode to detect the occurrence of an interrupt during the execution of a set of instructions. According to a preferred method of the present invention, the LOADALL instruction is used to load the code segment selector with the segment address of the code in the interrupted routine to be executed upon return from an interrupt and to load the code segment base address with the segment base address of the set of instruction during whose execution interrupt is to be detected. A preferred method then executes the set of instructions. Upon occurrence of an interrrupt, the preferred method saves the value in the code segment selector and executes an interrupt routine. Upon return from the interrupt routine, a preferred method loads the code segment base address based on the saved code segment value so that the interrupted routine resumes execution at an instruction other than the interrupted instruction. The methods of the present invention allow a program executing in real mode to access data in extended memory with interrupts enabled.
Inventors
- 👤 Scott A. Randell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:39
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
146 words
A method of detecting the occurrence of an interrupt during the execution of a set of instructions on a processor with a code segment selector register and a code segment base address register, the method comprising the steps of: loading the code segment selector register with the segment address of interrupt processing code to be executed upon completion of an interrupt routine; loading the code segment base address register with the segment base address of the set of instructions; executing the set of instructions; upon the occurrence of an interrupt during the execution of the set of instruction, saving the value of the code segment selector register and executing an interrupt routine; and upon return from the executed interrupt routine, loading the code segment base address register based on the saved value of the code segment selector register so that the interrupt processing code is executed.
Claim 2
Independent Claim
146 words
A method of detecting the occurrence of an interrupt during the execution of a set of instructions on a processor with a code segment selector register and a code segment base address register, the method comprising the steps of: loading the code segment selector register with the segment address of interrupt processing code to be executed upon completion of an interrupt routine; loading the code segment base address register with the segment base address of the set of instructions; executing the set of instructions; upon the occurrence of an interrupt during the execution of the set of instruction, saving the value of the code segment selector register and executing an interrupt routine; and upon return from the executed interrupt routine, loading the code segment base address register based on the saved value of the code segment selector register so that the interrupt processing code is executed.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein the processor is an Intel 80286.
Claim 4
Dependent Claim
13 words
The method of claim 1 wherein the processor is compatible the Intel 80286.
Claim 5
Dependent Claim
14 words
The method of claim 1 wherein the set of instructions includes an interruptible instruction.
Claim 6
Dependent Claim
13 words
The method of claim 4 wherein the interruptible instruction is a repeat instruction.
Claim 7
Independent Claim
204 words
A method of accessing data in extended memory with interrupts enabled on an Intel 80286-compatible based computer with A20 enabled, the method comprising the steps of: disabling the interrupts; loading the portion of the LoadAll Buffer corresponding to the CS Selector with the segment address of code to be executed when an interrupt occurs during execution of code that accesses extended memory; loading the portion of the LoadAll Buffer corresponding to the CS Segment Base Address with the segment base address of the code segment of the code that accesses extended memory; loading the portion of the LoadAll Buffer corresponding to a non-CS Segment Base Address with the segment base address of the data to be accessed in extended memory; executing the LoadAll instruction; enabling the interrupts; executing the code that accesses extended memory; upon occurrence of an interrupt during the execution of the code that accesses extended memory, saving the value of the CS Selector; executing an interrupt routine; upon return from the interrupt routine, loading the CS Segment Base Address based on the saved CS Selector value; and executing instructions to reset the state of the CPU so that the execution of the interrupted code that accesses extended memory can be continued.
Claim 8
Independent Claim
204 words
A method of accessing data in extended memory with interrupts enabled on an Intel 80286-compatible based computer with A20 enabled, the method comprising the steps of: disabling the interrupts; loading the portion of the LoadAll Buffer corresponding to the CS Selector with the segment address of code to be executed when an interrupt occurs during execution of code that accesses extended memory; loading the portion of the LoadAll Buffer corresponding to the CS Segment Base Address with the segment base address of the code segment of the code that accesses extended memory; loading the portion of the LoadAll Buffer corresponding to a non-CS Segment Base Address with the segment base address of the data to be accessed in extended memory; executing the LoadAll instruction; enabling the interrupts; executing the code that accesses extended memory; upon occurrence of an interrupt during the execution of the code that accesses extended memory, saving the value of the CS Selector; executing an interrupt routine; upon return from the interrupt routine, loading the CS Segment Base Address based on the saved CS Selector value; and executing instructions to reset the state of the CPU so that the execution of the interrupted code that accesses extended memory can be continued.
Claim 9
Dependent Claim
17 words
The method of claim 6 wherein the code that accesses the extended memory is the repeat instruction.
Claim 10
Dependent Claim
18 words
The method of claim 6 wherein the code that accesses extended memory consists of a set of instructions.
Claim 11
Independent Claim
109 words
A method in a computer system, supporting interrupts and having predetermined system interrupt routines to process the interrupts, of returning from the execution of an interrupt routine at an alternate location that is other than the interrupted location, the method comprising the steps of: loading a register with a value indicating the address of the alternate location; storing interrupt processing .code to be executed upon return from the interrupt routine at the alternate location; executing a set of instructions; and upon occurrence of an interrupt, executing a system interrupt routine; and upon completion of a system interrupt routine, returning to the alternate location thereby executing the interrupt processing code.
Claim 12
Independent Claim
109 words
A method in a computer system, supporting interrupts and having predetermined system interrupt routines to process the interrupts, of returning from the execution of an interrupt routine at an alternate location that is other than the interrupted location, the method comprising the steps of: loading a register with a value indicating the address of the alternate location; storing interrupt processing .code to be executed upon return from the interrupt routine at the alternate location; executing a set of instructions; and upon occurrence of an interrupt, executing a system interrupt routine; and upon completion of a system interrupt routine, returning to the alternate location thereby executing the interrupt processing code.
Claim 13
Dependent Claim
75 words
The method of claim 9 wherein the computer system is based upon an Intel 80286-compatible processor and the register is the code segment register, and wherein the step of loading the register further comprises the steps of: loading the portion of the LoadAll Buffer corresponding to the CS Selector with the segment address of the alternate location; and executing the LoadAll instruction thereby loading the CS Selector with the segment address of the alternate location.
Claim 14
Independent Claim
151 words
An apparatus for detecting an occurrence of an interrupt during the execution of a set of instructions on a processor with a code segment selector register and a code segment base address register comprising: means for loading the code segment selector register with the segment address of interrupt processing code to be executed upon completion of an interrupt routine; means for loading the code segment base address register with the segment base address of the set of instruction; means for executing the set of instructions; means for, upon the occurrence of an interrupt during the execution of the set of instructions, saving the value of the code segment selector register and executing an interrupt routine; and means for, upon return from the executed interrupt routine, loading the code segment base address register based on the saved value of the code segment selector register so that the interrupt processing code is executed.
Claim 15
Independent Claim
151 words
An apparatus for detecting an occurrence of an interrupt during the execution of a set of instructions on a processor with a code segment selector register and a code segment base address register comprising: means for loading the code segment selector register with the segment address of interrupt processing code to be executed upon completion of an interrupt routine; means for loading the code segment base address register with the segment base address of the set of instruction; means for executing the set of instructions; means for, upon the occurrence of an interrupt during the execution of the set of instructions, saving the value of the code segment selector register and executing an interrupt routine; and means for, upon return from the executed interrupt routine, loading the code segment base address register based on the saved value of the code segment selector register so that the interrupt processing code is executed.
Claim 16
Dependent Claim
12 words
The apparatus of claim 11 wherein the processor is an Intel 80286.
Claim 17
Dependent Claim
13 words
The apparatus of claim 11 wherein the processor is compatible the Intel 80286.
Claim 18
Dependent Claim
14 words
The apparatus of claim 11 wherein the set of instructions includes an interruptible instruction.
Claim 19
Dependent Claim
13 words
The apparatus of claim 14 wherein the interruptible instruction is a repeat instruction.
Claim 20
Independent Claim
216 words
An apparatus for accessing data in extended memory with interrupts enabled on an Intel 80286-compatible based computer with A20 enabled comprising: means for disabling the interrupts; means for loading the portion of the LoadAll Buffer corresponding to the CS Selector with the segment address of code to be executed when an interrupt occurs during execution of code that accesses extended memory; means for loading the portion of the LoadAll Buffer corresponding to the CS Segment Base Address with the segment base address of the code segment of the code that accesses extended memory; means for loading the portion of the LoadAll Buffer corresponding to a non-CS Segment Base Address with the segment base address of the data to be accessed in extended memory; means for executing the LoadAll instruction; means for enabling the interrupts; means for executing the code that accesses extended memory; means for, upon occurrence of an interrupt during the execution of the code that accesses extended memory, saving the value of the CS Selector; executing an interrupt routine; and upon return from the interrupt routine, loading the CS Segment Base Address based on the saved CS Selector value; and executing instructions to reset the state of the CPU so that the execution of the interrupted code that accesses extended memory can be continued.
Claim 21
Independent Claim
216 words
An apparatus for accessing data in extended memory with interrupts enabled on an Intel 80286-compatible based computer with A20 enabled comprising: means for disabling the interrupts; means for loading the portion of the LoadAll Buffer corresponding to the CS Selector with the segment address of code to be executed when an interrupt occurs during execution of code that accesses extended memory; means for loading the portion of the LoadAll Buffer corresponding to the CS Segment Base Address with the segment base address of the code segment of the code that accesses extended memory; means for loading the portion of the LoadAll Buffer corresponding to a non-CS Segment Base Address with the segment base address of the data to be accessed in extended memory; means for executing the LoadAll instruction; means for enabling the interrupts; means for executing the code that accesses extended memory; means for, upon occurrence of an interrupt during the execution of the code that accesses extended memory, saving the value of the CS Selector; executing an interrupt routine; and upon return from the interrupt routine, loading the CS Segment Base Address based on the saved CS Selector value; and executing instructions to reset the state of the CPU so that the execution of the interrupted code that accesses extended memory can be continued.
Claim 22
Dependent Claim
17 words
The apparatus of claim 16 wherein the code that accesses the extended memory is the repeat instruction.
Claim 23
Dependent Claim
18 words
The apparatus of claim 16 wherein the code that accesses extended memory consists of a set of instructions.
Claim 24
Independent Claim
111 words
An apparatus based upon a computer system, supporting interrupts and having predetermined system interrupt routines to process the interrupts, for returning from the execution of an interrupt routine at an alternate location that is other than the interrupted location comprising: means for loading a register with a value indicating the address of the alternate location; means for storing interrupt processing code to be executed upon return from the interrupt routine at the alternate location; means for executing a set of instructions; and means for, upon occurrence of an interrupt, executing the interrupt routine; and upon completion of the interrupt routine, returning to the alternate location thereby executing the interrupt processing code.
Claim 25
Independent Claim
111 words
An apparatus based upon a computer system, supporting interrupts and having predetermined system interrupt routines to process the interrupts, for returning from the execution of an interrupt routine at an alternate location that is other than the interrupted location comprising: means for loading a register with a value indicating the address of the alternate location; means for storing interrupt processing code to be executed upon return from the interrupt routine at the alternate location; means for executing a set of instructions; and means for, upon occurrence of an interrupt, executing the interrupt routine; and upon completion of the interrupt routine, returning to the alternate location thereby executing the interrupt processing code.
Claim 26
Dependent Claim
76 words
The apparatus of claim 19 wherein the computer system is based upon an Intel 80286-compatible processor and the register is the code segment register, and wherein the means for loading the register further comprises: means for loading the portion of the LoadAll Buffer corresponding to the CS Selector with the segment address of the alternate location; and means for executing the LoadAll instruction thereby loading the CS Selector with the segment address of the alternate location.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |