US4807185A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stack pointer control circuit
Assignee: Toshiba Corp
•
Filing: 1986-12-04
•
Granted: 1989-02-21
•
Expires: 2006-12-04
Abstract
Abstract In the conventional CPU, when an interruption occurs during execution of a stack control instruction, the interrupted stack control instruction is executed again beginning from the start, so that a stack memory address currently designated by the stack pointer does not match that corresponding to the start of the instruction execution, thus resulting in a program error. To overcome the above problem, at the start of information saving and/or return operation, a stack memory address stored in the first register so as to be read next is additionally stored in the second register. Although the above operation is executed on the basis of the stack memory address stored in the first register, in case an interrupt occurs, the stack memory address stored in the second register is set to the first register before executing again the interrupted stack control instruction.
Inventors
- 👤 Shigeo Kamiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:49
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/461
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
185 words
A stack pointer control circuit for designating stack memory addresses to save and/or return information, from a predetermined register to a stack memory or vice versa, which comprises: (a) first register means for storing a stack memory address to be read next; (b) updating means for updating the address stored in said first register means; (c) second register means for storing a same stack memory address as that stored in said first register means at a start of an information saving and/or return operation; (d) setting means for setting the same stack memory address as that stored in said first register means to said second register means at the start of an information saving and/or return operation; (e) designating means for designating a stack memory address stored in said first register means in response to an information saving and/or return operation start signal for the information saving and/or return operation; and (f) stopped address processing means for setting an address stored in said second register means to said first register means in response to a stop signal generated during the information saving and/or return operation.
Claim 2
Dependent Claim
185 words
A stack pointer control circuit for designating stack memory addresses to save and/or return information, from a predetermined register to a stack memory or vice versa, which comprises: (a) first register means for storing a stack memory address to be read next; (b) updating means for updating the address stored in said first register means; (c) second register means for storing a same stack memory address as that stored in said first register means at a start of an information saving and/or return operation; (d) setting means for setting the same stack memory address as that stored in said first register means to said second register means at the start of an information saving and/or return operation; (e) designating means for designating a stack memory address stored in said first register means in response to an information saving and/or return operation start signal for the information saving and/or return operation; and (f) stopped address processing means for setting an address stored in said second register means to said first register means in response to a stop signal generated during the information saving and/or return operation.
Claim 3
Dependent Claim
43 words
The stack pointer control circuit as set forth in claim 1, wherein said updating means comprises an adder/subtracter circuit for counting up or down from an address stored in said first register means and setting the counted address to said first register means.
Claim 4
Dependent Claim
55 words
The stack pointer control circuit as set forth in claim 1, wherein said designating means and said stopped address processing means are a first selector circuit provided on an address input side of said first register means and second and third selector circuit provided on an address output side of said first register means, respectively.
Claim 5
Dependent Claim
31 words
The stack pointer control circuit as set forth in claim 3, wherein said setting means is the second selector circuit provided on an address input side of said second register means.
Claim 6
Dependent Claim
24 words
The stack pointer control circuit as set forth in claim 1, wherein the stop signal is an interrupt signal generated when an interruption occurs.
Claim 7
Dependent Claim
39 words
The stack pointer control circuit as set forth in claim 5, wherein the designating or setting are done by said stopped address processing means when the information saving and/or return operation is reexecuted after an interruption has been processed.
Claim 8
Dependent Claim
69 words
The stack pointer control circuit as set forht in claim 1, which further comprises: (a) state setting means for setting a first state and a second state alternately whenever the stop signal is supplied thereto; and (b) operation exchange means for controlling said first register means and said second register means so that operating of both said register means are exchanged whenever said state setting means changes in state.
Claim 9
Dependent Claim
156 words
A stack pointer control circuit for saving a value from a predetermined register to a stack memory and returning the value read out of the stack memory to the predetermined register, which comprises: (a) first register means for storing a stack memory address to be read next; (b) second register means for storing an address stored in said first register means at a start of a saving or return operation; (c) control means for saving a value stored in the predetermined register to the stack memory in response to the address stored in said first register means and for returning the value read out of the stack memory to the predetermined register in response to the address stored in said first register means; and (d) stopped address processing means for setting a value in said second register means to said first register means in response to a stop signal generated during the saving or return operation.
Claim 10
Dependent Claim
156 words
A stack pointer control circuit for saving a value from a predetermined register to a stack memory and returning the value read out of the stack memory to the predetermined register, which comprises: (a) first register means for storing a stack memory address to be read next; (b) second register means for storing an address stored in said first register means at a start of a saving or return operation; (c) control means for saving a value stored in the predetermined register to the stack memory in response to the address stored in said first register means and for returning the value read out of the stack memory to the predetermined register in response to the address stored in said first register means; and (d) stopped address processing means for setting a value in said second register means to said first register means in response to a stop signal generated during the saving or return operation.
Claim 11
Dependent Claim
113 words
The stack pointer control circuit as set forth in claim 8, wherein said control means comprises: (a) state setting means for setting a first state and a second state alternately whenever the stop signal is supplied thereto; (b) operation exchange means for controlling said first register means and said second register means so that operations of both said register means are exchanged when said state setting means is at the second state; and wherein said stopped address processing means being activated when a value is exchanged between said first register means and said second register means by said state setting means and said operation exchange means reversed whenever the stop signal is supplied.
References Cited (Backward Citations)
US4268903A
Cited
US4451891A
Cited
US4524416A
Cited
US4438492A
Cited
US4459657A
Cited
US4445190A
Cited
US4443865A
Cited
US4484274A
Cited
US4607332A
Cited
US4736317A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |