US5124770A — Field effect transistor with alpha particle prote…

Claim 1

Independent Claim 320 words

A field effect transistor comprising: a compound semiconductor substrate of a second conductivity type; an element region disposed in a surface region of said semiconductor substrate, said element region comprising a source region and a drain region, both source and drain regions being of a first conductivity type opposite to said second conductivity type, and separated from each other, and an active region disposed between the source and drain regions; and a semiconductor structure disposed in said substrate between a remaining portion of said substrate and said element region, said remaining portion of said substrate being a portion other than said element region and semiconductor structure; said semiconductor structure comprising at least one layer of said second conductivity type and at least one layer of a third conductivity type, the third conductivity type being the same as the first conductivity type; said at least one layer of second conductivity type being positioned between said element region and said at least one layer of third conductivity type, and said at least one layer of third conductivity type being between said remaining portion and said at least one layer of second conductivity type; the at least one layer of second conductivity type and the at least one layer of third conductivity type in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, so as to block flow of electrons into one of the at least one layer of second conductivity type and the at least one layer of third conductivity type and to block flow of holes into another of the at least one layer of second conductivity type and the at least one layer of third conductivity type, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region, is suppressed.

Claim 2

Dependent Claim 320 words

A field effect transistor comprising: a compound semiconductor substrate of a second conductivity type; an element region disposed in a surface region of said semiconductor substrate, said element region comprising a source region and a drain region, both source and drain regions being of a first conductivity type opposite to said second conductivity type, and separated from each other, and an active region disposed between the source and drain regions; and a semiconductor structure disposed in said substrate between a remaining portion of said substrate and said element region, said remaining portion of said substrate being a portion other than said element region and semiconductor structure; said semiconductor structure comprising at least one layer of said second conductivity type and at least one layer of a third conductivity type, the third conductivity type being the same as the first conductivity type; said at least one layer of second conductivity type being positioned between said element region and said at least one layer of third conductivity type, and said at least one layer of third conductivity type being between said remaining portion and said at least one layer of second conductivity type; the at least one layer of second conductivity type and the at least one layer of third conductivity type in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, so as to block flow of electrons into one of the at least one layer of second conductivity type and the at least one layer of third conductivity type and to block flow of holes into another of the at least one layer of second conductivity type and the at least one layer of third conductivity type, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region, is suppressed.

Claim 3

Dependent Claim 14 words

A field effect transistor according to claim 1, wherein the semiconductor substrate is semi-insulating.

Claim 4

Dependent Claim 75 words

A field effect transistor according to claim 1, wherein said semiconductor structure has a minimum value of electron affinity that is smaller than a value of electron affinity in said remaining portion of said substrate, and said semiconductor structure has a maximum value of the sum of electron affinity and forbidden band width greater than a maximum value of the sum of electron affinity and forbidden band width in said remaining portion of said substrate.

Claim 5

Dependent Claim 52 words

A field effect transistor according to claim 1, wherein the flow of electrons and holes in the at least one layer of second conductivity type and into the at least one layer of third conductivity type is blocked such that both electrons and holes remain in the remaining portion of the substrate.

Claim 6

Dependent Claim 78 words

A field effect transistor according to claim 1, wherein the semiconductor structure, comprising said at least one layer of a second conductivity type and said at least one layer of a third conductivity type, is disposed in said substrate between the remaining portion of said substrate and said element region such that both electrons and holes generated in the remaining portion of the substrate remain in the remaining portion of the substrate and are annihilated through recombination thereof.

Claim 7

Dependent Claim 177 words

A field effect transistor comprising: an n-type compound semiconductor substrate; an element region disposed in a surface region of said substrate and including n-type source and drain regions and an active region between said source and drain regions; a p-type semiconductor layer disposed in the substrate between a remaining portion of the substrate and said element region; and an n + -region semiconductor layer disposed between said remaining portion of the substrate and said p-type semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, said remaining portion of the substrate being a portion other than the p-type semiconductor layer, said n + -type semiconductor layer and the element region, the p-type semiconductor layer and n + -type semiconductor layer in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region is suppressed.

Claim 8

Dependent Claim 177 words

A field effect transistor comprising: an n-type compound semiconductor substrate; an element region disposed in a surface region of said substrate and including n-type source and drain regions and an active region between said source and drain regions; a p-type semiconductor layer disposed in the substrate between a remaining portion of the substrate and said element region; and an n + -region semiconductor layer disposed between said remaining portion of the substrate and said p-type semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, said remaining portion of the substrate being a portion other than the p-type semiconductor layer, said n + -type semiconductor layer and the element region, the p-type semiconductor layer and n + -type semiconductor layer in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region is suppressed.

Claim 9

Dependent Claim 59 words

A field effect transistor according to claim 6, wherein the p-type semiconductor layer and n + -type semiconductor layer in combination serve as potential barriers to the flow of both electrons and holes so as to substantially block flow of electrons into the p-type semiconductor layer and substantially block flow of holes into the n + -type semiconductor layer.

Claim 10

Dependent Claim 136 words

A field effect transistor comprising: a semiconductor substrate; a first compound semiconductor layer formed on said substrate; an element region formed in said first semiconductor layer, said element region including source and drain regions and an active region between the source and the drain regions; and a second semiconductor layer disposed between said substrate and said first semiconductor layer and having a wider band gap than that of said substrate such that the second semiconductor layer serves as a potential barrier to the flow of both electrons and holes from the substrate to the element region, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the substrate into the element region is suppressed, the element region, formed in the first semiconductor layer, being spaced from the second semiconductor layer.

Claim 11

Dependent Claim 136 words

A field effect transistor comprising: a semiconductor substrate; a first compound semiconductor layer formed on said substrate; an element region formed in said first semiconductor layer, said element region including source and drain regions and an active region between the source and the drain regions; and a second semiconductor layer disposed between said substrate and said first semiconductor layer and having a wider band gap than that of said substrate such that the second semiconductor layer serves as a potential barrier to the flow of both electrons and holes from the substrate to the element region, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the substrate into the element region is suppressed, the element region, formed in the first semiconductor layer, being spaced from the second semiconductor layer.

Claim 12

Dependent Claim 41 words

A field effect transistor according to claim 8, wherein said semiconductor substrate is made of semi-insulating GaAs, said first semiconductor layer is made of GaAs, said element region is made of GaAs and said second semiconductor layer is made of GaAlAs.

Claim 13

Dependent Claim 34 words

A field effect transistor according to claim 9, wherein the GaAs first semiconductor layer is undoped, wherein the GaAs element region is of n-type conductivity and wherein the GaAlAs second semiconductor layer is undoped.

Claim 14

Dependent Claim 21 words

A field effect transistor according to claim 8, wherein the element region extends to a surface of the first semiconductor layer.

Claim 15

Dependent Claim 24 words

A field effect transistor according to claim 8, wherein the element region is of n-conductivity type, and wherein said second semiconductor layer is undoped.

Claim 16

Dependent Claim 19 words

A field effect transistor according to claim 8, wherein the second semiconductor layer forms a heterojunction with the substrate.

Claim 17

Dependent Claim 44 words

A field effect transistor according to claim 13, wherein the second semiconductor layer has a band gap wider than that of the substrate such that both electrons and holes are blocked from flowing into the second semiconductor layer and therethrough to the element regions.

Claim 18

Dependent Claim 32 words

A field effect transistor according to claim 14, wherein the band gap of the second semiconductor layer is wider than the band gap of the substrate and of the first semiconductor layer.

Claim 19

Dependent Claim 32 words

A field effect transistor according to claim 8, wherein the band gap of the second semiconductor layer is wider than the band gap of the substrate and of the first semiconductor layer.

Claim 20

Dependent Claim 38 words

A field effect transistor according to claim 8, wherein said second semiconductor layer, having said wider band gap than that of said substrate, blocks flow of both holes and electrons from the substrate into the second semiconductor layer.

Claim 21

Dependent Claim 33 words

A field effect transistor according to claim 8, wherein a conductivity type of the source and drain regions of said element region is the same as a conductivity type of said active region.

Claim 22

Dependent Claim 54 words

A field effect transistor according to claim 8, wherein the second semiconductor layer is disposed between said substrate and said first semiconductor layer, and has said wider band gap, such that said electrons and holes, formed by incidence of α- particles on the substrate, remain in the substrate and are annihilated by recombination thereof.

Claim 23

Dependent Claim 244 words

A field effect transistor comprising: a semi-insulating compound semiconductor substrate; an element region disposed in a surface region of the semiconductor substrate, the element region comprising a source region and a drain region, both of a first conductivity type and separated from each other, with an active region disposed between the source region and the drain region; and a semiconductor structure disposed in the substrate between a remaining portion of the substrate and said element region, said remaining portion of the substrate being a portion other than the element region and semiconductor structure, the semiconductor structure comprising at least one layer of second conductivity type opposite said first conductivity type and at least one layer of first conductivity type, said at least one layer of second conductivity type being positioned between said element region and said at least one layer of first conductivity type, and said at least one layer of first conductivity type being between said remaining portion of the substrate and said at least one layer of second conductivity type, the at least one layer of second conductivity type and the at least one layer of first conductivity type in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region is suppressed.

Claim 24

Dependent Claim 244 words

A field effect transistor comprising: a semi-insulating compound semiconductor substrate; an element region disposed in a surface region of the semiconductor substrate, the element region comprising a source region and a drain region, both of a first conductivity type and separated from each other, with an active region disposed between the source region and the drain region; and a semiconductor structure disposed in the substrate between a remaining portion of the substrate and said element region, said remaining portion of the substrate being a portion other than the element region and semiconductor structure, the semiconductor structure comprising at least one layer of second conductivity type opposite said first conductivity type and at least one layer of first conductivity type, said at least one layer of second conductivity type being positioned between said element region and said at least one layer of first conductivity type, and said at least one layer of first conductivity type being between said remaining portion of the substrate and said at least one layer of second conductivity type, the at least one layer of second conductivity type and the at least one layer of first conductivity type in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region is suppressed.

Claim 25

Dependent Claim 40 words

A field effect transistor according to claim 20, wherein said at least one layer of second conductivity type and said at least one layer of first conductivity type include at least one n-type layer and at least one p-type layer.

Claim 26

Dependent Claim 45 words

A field effect transistor according to claim 20, wherein said at least one layer of second conductivity type is a p-type layer, said at least one layer of first conductivity type is an n-type layer, and the source and drain regions are n-type conductivity regions.

Claim 27

Dependent Claim 28 words

A field effect transistor according to claim 22, wherein the doping impurity for the p-type layer is selected from the group consisting of Be, Mg, C and Zn.

Claim 28

Dependent Claim 27 words

A field effect transistor according to claim 23, wherein the doping impurity for the n-type layer is selected from the group consisting of Si, Se and S.

Claim 29

Dependent Claim 77 words

A field effect transistor according to claim 20, wherein the semiconductor structure, comprising said at least one layer of a second conductivity type and said at least one layer of a first conductivity type, is disposed in said substrate between the remaining portion of said substrate and said element region such that both electrons and holes from the remaining portion of the substrate remain in the remaining portion of the substrate and are annihilated through recombination thereof.

Claim 30

Dependent Claim 185 words

A field effect transistor comprising: a p-type compound semiconductor substrate; an element region disposed in a surface region of said substrate and including p-type source and drain regions and an active region between said source and drain regions; an n-type semiconductor layer disposed in the substrate between a remaining portion of said substrate and said element region; and a p + -type semiconductor layer disposed in the substrate between said remaining portion of the substrate and said n-type semiconductor layer, said remaining portion of the substrate being a portion other than said element region, said p + -type semiconductor layer and said n-type semiconductor layer, said p + -type semiconductor layer having an impurity concentration higher than that of said semiconductor substrate, the n-type semiconductor layer and p + -type semiconductor layer in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region, is suppressed.

Claim 31

Dependent Claim 185 words

A field effect transistor comprising: a p-type compound semiconductor substrate; an element region disposed in a surface region of said substrate and including p-type source and drain regions and an active region between said source and drain regions; an n-type semiconductor layer disposed in the substrate between a remaining portion of said substrate and said element region; and a p + -type semiconductor layer disposed in the substrate between said remaining portion of the substrate and said n-type semiconductor layer, said remaining portion of the substrate being a portion other than said element region, said p + -type semiconductor layer and said n-type semiconductor layer, said p + -type semiconductor layer having an impurity concentration higher than that of said semiconductor substrate, the n-type semiconductor layer and p + -type semiconductor layer in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region, is suppressed.

Claim 32

Dependent Claim 59 words

A field effect transistor according to claim 26, wherein the n-type semiconductor layer and p + -type semiconductor layer in combination serve as potential barriers to the flow of both electrons and holes so as to substantially block flow of electrons into the p + -type semiconductor layer and substantially block flow of holes into the n-type semiconductor layer.

Claim 33

Dependent Claim 280 words

A field effect transistor comprising: a compound semiconductor substrate; an element region disposed in a surface region of said semiconductor substrate, said element region comprising a source region and a drain region, both source and drain regions being of a first conductivity type and separated from each other, and an active region disposed between the source and drain regions; and a semiconductor structure disposed in said substrate between a remaining portion of said substrate and said element region, said remaining portion of said substrate being a portion other than said element region and semiconductor structure; said semiconductor structure comprising at least one layer of second conductivity type opposite said first conductivity type and at least one layer of a third conductivity type, the third conductivity type being the same as the first conductivity type; said at least one layer of second conductivity type being positioned between said element region and said at least one layer of third conductivity type, and said at least one layer of third conductivity type being between said remaining portion and said at least one layer of second conductivity type; the at least one layer of second conductivity type and the at least one layer of third conductivity type in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, so as to block the flow of electrons and holes such that both electrons and holes remain in the remaining portion of the substrate, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region, is suppressed.

Claim 34

Dependent Claim 280 words

A field effect transistor comprising: a compound semiconductor substrate; an element region disposed in a surface region of said semiconductor substrate, said element region comprising a source region and a drain region, both source and drain regions being of a first conductivity type and separated from each other, and an active region disposed between the source and drain regions; and a semiconductor structure disposed in said substrate between a remaining portion of said substrate and said element region, said remaining portion of said substrate being a portion other than said element region and semiconductor structure; said semiconductor structure comprising at least one layer of second conductivity type opposite said first conductivity type and at least one layer of a third conductivity type, the third conductivity type being the same as the first conductivity type; said at least one layer of second conductivity type being positioned between said element region and said at least one layer of third conductivity type, and said at least one layer of third conductivity type being between said remaining portion and said at least one layer of second conductivity type; the at least one layer of second conductivity type and the at least one layer of third conductivity type in combination serving as potential barriers to the flow of both electrons and holes from the remaining portion of the substrate to the element region, so as to block the flow of electrons and holes such that both electrons and holes remain in the remaining portion of the substrate, whereby injection of both holes and electrons, formed by incidence of α-particles on the substrate, from the remaining portion of the substrate into the element region, is suppressed.

Claim 35

Dependent Claim 77 words

A field effect transistor according to claim 28, wherein the semiconductor structure, comprising said at least one layer of a second conductivity type and said at least one layer of a first conductivity type, is disposed in said substrate between the remaining portion of said substrate and said element region such that both electrons and holes from the remaining portion of the substrate remain in the remaining portion of the substrate and are annihilated through recombination thereof.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1995-06-23	1995-12-23	1996-06-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1999-06-23	1999-12-23	2000-06-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2003-06-23	2003-12-23	2004-06-23	$7700.00	Window Closed / Lapsed

Field effect transistor with alpha particle protection

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