Semiconductor memory device with individually addressable space cells capable of driving a data bus

Claim 2

A semiconductor memory device, comprising: a memory array including a plurality of memory cells; addressing means responsive to externally applied row and column address signals for designating an individual memory cell in the memory array; redundant circuit means, located on a portion of said memory device which is logically and physically separated from said memory array and including a spare memory cell for selective substitution for an individual defective memory cell in said memory array; programming means for previously programming row and column address signals designating said individual defective memory cell in said memory array; and substitution control means connected to said addressing means and said programming means for functionally substituting said spare memory cell for the individual defective memory cell in said memory array when externally applied row and column address signals supplied from said addressing means are coincident with the previously programmed row and column addresses of said individual defective memory cell.

Claim 3

The semiconductor memory device according to claim 1, wherein: said redundant circuit means includes writing means connected to receive an input data signal for selectively writing said input data signal in said spare memory cell responsive to a control signal from said substitution control means.

Claim 4

The semiconductor memory device according to claim 1, wherein: said substitution control means includes first and second switching means, both of which operate responsive to said addressing signals. said first switching means receiving and outputting a read-out signal from said memory array, and said second switching means receiving and outputting a read-out signal from said spare memory cell.

Claim 5

The semiconductor memory device according to claim 1, wherein: said programming means includes an address switching circuit means for receiving an address signal and converting said address signal in accordance with a program previously stored therein.

Claim 6

The semiconductor memory device according to claim 1, wherein: said spare memory cell includes flip-flop means constituted by two inverter means.

Claim 7

The semiconductor memory device according to claim 1, wherein: the semiconductor memory device includes a static semiconductor memory device.

Claim 8

The semiconductor memory device according to claim 1, wherein: said semiconductor memory device includes a mask read only memory device.

Claim 9

The semiconductor memory device according to claim 2, wherein: said writing means includes two cascaded inverters, and a third switching means connected between said cascaded inverters and said spare memory cell for operating responsive to a control signal from said substitution control means.

Claim 10

In a semiconductor memory device having an array of memory cells and a spare cell for substitution for a defective memory cell of said array, the improvement comprising: addressing means for individually addressing by row and column one of said memory cells of said array, programming means for previously programming row and column address signals designating an individual defective memory cell in said array; and switching means for switchably connecting said spare cell to a read data bus in substitution for said defective memory cell of said array in response to externally applied row and column address signals supplied from said addressing means and coinciding with the row and column address signals for the defective cell previously programmed by said programming means.

Claim 11

In a semiconductor memory device having an array of memory cells and a spare cell for substitution for a defective memory cell of said array, the improvement comprising: addressing means for individually addressing by row and column one of said memory cells of said array, programming means for previously programming row and column address signals designating an individual defective memory cell in said array; and switching means for switchably connecting said spare cell to a read data bus in substitution for said defective memory cell of said array in response to externally applied row and column address signals supplied from said addressing means and coinciding with the row and column address signals for the defective cell previously programmed by said programming means.

Claim 12

The improved semiconductor memory device according to claim 9, wherein said spare cell comprises inverter means for amplifying data read out therefrom for provision of the amplified data to the read data bus, whereby a requirement for a separate sense amplifier is eliminated and a delay associated with processing of the read out data by a sense amplifier is eliminated.

Claim 13

The improved semiconductor memory device according to claim 10, wherein said inverter means comprises inverters connected in a flip flop configuration to provide the amplifier data read out from the spare cell to the read data bus.

Claim 14

The improved semiconductor memory device according to claim 9, further comprising transmission gate means for directly connecting an output from an inverter means in said spare cell to the read data bus.

Claim 15

The improved semiconductor memory device according to claim 9, wherein said spare cell is located on said memory device at a position logically and physically separated from said array of memory cells.

Claim 16

In a semiconductor memory device having an array of memory cells and a spare cell for substitution for a defective memory cell of said array, the improvement comprising: addressing means for individually addressing, by row and column, one of said memory cells of said array, programming means for previously programming row and column address signals designating a single defective memory cell in said array; and switching means for switchably connecting said spare cell in substitution for said single defective memory cell of said array in response cell to said address means providing row and column address signals coinciding with the row and column address signals for said single defective memory cell previously programmed by said programming means, said spare cell comprising inverter means for amplifying data read out therefrom for provision of the amplified data to a read data bus, whereby a requirement for a separate sense amplifier is eliminated and a delay associated with amplification of the read out data by a sense amplifier is eliminated.

Claim 17

In a semiconductor memory device having an array of memory cells and a spare cell for substitution for a defective memory cell of said array, the improvement comprising: addressing means for individually addressing, by row and column, one of said memory cells of said array, programming means for previously programming row and column address signals designating a single defective memory cell in said array; and switching means for switchably connecting said spare cell in substitution for said single defective memory cell of said array in response cell to said address means providing row and column address signals coinciding with the row and column address signals for said single defective memory cell previously programmed by said programming means, said spare cell comprising inverter means for amplifying data read out therefrom for provision of the amplified data to a read data bus, whereby a requirement for a separate sense amplifier is eliminated and a delay associated with amplification of the read out data by a sense amplifier is eliminated.

Claim 18

The improved semiconductor memory device according to claim 14, wherein said inverter means of said spare cell are connected as a flip flop to provide the amplified data read out from the spare cell to the read data bus.

Claim 19

The improved semiconductor memory device according to claim 15, further comprising transmission gate means for directly connecting an output from a flip flop of said spare cell to the read data bus.

Claim 20

The improved semiconductor memory device according to claim 14, wherein said spare cell is located on a portion of said memory device which is logically and physically separated from said array of memory cells.

Claim 21

The improved semiconductor memory device according to claim 17, wherein said inverter means of said spare cell are connected as a flip flop to provide the amplified data read out from the spare cell to the read data bus.

Claim 22

The improved semiconductor memory device according to claim 18, further comprising transmission gate means for directly connecting an output from a flip flop of said spare cell to the read data bus.

Claim 23

In a semiconductor memory device having an array of memory cells arranged in rows and columns and having a spare memory cell for substitution for a defective memory cell of said array, a method for replacing the defective cell of said array comprising the steps of: identifying an individual defective memory cell by row and column information; programming row and column address signals designating said individual defective memory cell; and in response to address signals which correspond to the programmed row and column address signals for said individual defective memory cell, address said spare cell and substituting said spare cell for said individual defective memory cell for subsequent memory operation.

Claim 24

In a semiconductor memory device having an array of memory cells arranged in rows and columns and having a spare memory cell for substitution for a defective memory cell of said array, a method for replacing the defective cell of said array comprising the steps of: identifying an individual defective memory cell by row and column information; programming row and column address signals designating said individual defective memory cell; and in response to address signals which correspond to the programmed row and column address signals for said individual defective memory cell, address said spare cell and substituting said spare cell for said individual defective memory cell for subsequent memory operation.

Claim 25

A semiconductor memory device, comprising: a memory array including a plurality of memory cells; addressing means responsive to externally applied row and column address signals for designating an individual memory cell in the memory array; redundant circuit means, located on a portion of said memory device which is logically and physically separated from said memory array and including a spare memory cell for selective substitution for an individual defective memory cell in said memory array; programming means for previously programming row and column address signals designating said individual defective memory cell in said memory array; row and column address coincidence detecting means for detecting a coincidence of the externally applied row and column address signals with the row and column address signals of said defective memory cell; and substitution control means connected to said addressing means and said programming means and responsive to said row and column address coincidence detecting means for functionally substituting said spare memory cell for the individual defective memory cell.

Claim 26

A semiconductor memory device, comprising: a memory array including a plurality of memory cells; addressing means responsive to externally applied row and column address signals for designating an individual memory cell in the memory array; redundant circuit means, located on a portion of said memory device which is logically and physically separated from said memory array and including a spare memory cell for selective substitution for an individual defective memory cell in said memory array; programming means for previously programming row and column address signals designating said individual defective memory cell in said memory array; row and column address coincidence detecting means for detecting a coincidence of the externally applied row and column address signals with the row and column address signals of said defective memory cell; and substitution control means connected to said addressing means and said programming means and responsive to said row and column address coincidence detecting means for functionally substituting said spare memory cell for the individual defective memory cell.