US5122687A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Symmetrical exclusive-or gate, and modification thereof to provide an analog multiplier
Assignee: Bosch Telecom GmbH
•
Filing: 1989-07-15
•
Granted: 1992-06-16
•
Expires: 2009-07-15
Abstract
Abstract An Exclusive-Or circuit has a symmetrical arrangement of components in order to provide an identical input impedance for both input signals and to provide identical switching and signal propagation times. The circuit includes input stages (EF 1 , EF 2 ; EF 3 , EF 4 ) for receiving first and second input signals (V E1 ; V E2 ) and emitter followers (EF 5 , EF 6 , EF 7 , EF 8 ) connected to the input stages. A current switch stage (T 11 , T 12 , T 13 , T 14 ) is driven by the input stage for the first input signal, and an identical current switch stage (T 21 , T 22 , T 23 , T 24 ) is driven by the input stage for the second input signal. These current switch stages are connected by load resistors (R 1 , R 1 ) to one pole of an operating voltage source (U B ). Another current switch stage (T 15 , T 16 ), is connected between a current source (I O /2) and the current switch stage (T 11 , T 12 , T 13 , T 14 ) that is driven by the input stage for the first input signal, and another identical current switch stage (T 25 , T 26 ) is connected between a further current source (I O 2) and the current switch stage (T 21 , T 22 , T 23 , T 24 ) that is driven by the input stage for the second input signal. These current switch stages (T 15 , T 16 , T 25 , T 26 ) are driven by the emitter followers (EF 5 , EF 6 ; EF 7 , EF 8 ) that are connected to the input stages. The current sources are connected to the other pole of the operating voltage source (U B ). A buffer stage (EF 9 , EF 10 , EF 11 , EF 12 ) connects the load resistors to a current switch (T 8 , T 9 ) which provides the output signal (U A ). An analog multiplier can be made by modifying this circuitry.
Inventors
- 👤 Lothar Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0866; H03K19/20; H03K19/21; H03K19/212
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
242 words
A circuit arrangement for Exclusively Or-ing first and second input signals, comprising: a first input stage which receives the first input signal, the first input stage including at least one transistor and at least one diode; at least one first emitter follower connected to the at least one diode of the first input stage; a second input stage which receives the second input signal, the second input stage including at least one transistor and at least one diode; at least one second emitter follower connected to the at least one diode of the second input stage; a pair of current sources; a first current switch stage connected to the first input stage; a second current switch stage connected to the second input stage, the second current switch stage having circuitry identical to the first current switch stage; another first current switch stage connected to the at least one first emitter follower, the another first current switch stage being connected between one of the current sources and the second current switch stage; another second current switch stage connected to the at least one second emitter follower, the another second current switch stage being connected between the other of the current sources and the first current switch stage, the another second current switch stage having circuitry identical to the another first current switch stage; and at least one load resistance member connected to the first current switch stage and the second current switch stage.
Claim 2
Dependent Claim
242 words
A circuit arrangement for Exclusively Or-ing first and second input signals, comprising: a first input stage which receives the first input signal, the first input stage including at least one transistor and at least one diode; at least one first emitter follower connected to the at least one diode of the first input stage; a second input stage which receives the second input signal, the second input stage including at least one transistor and at least one diode; at least one second emitter follower connected to the at least one diode of the second input stage; a pair of current sources; a first current switch stage connected to the first input stage; a second current switch stage connected to the second input stage, the second current switch stage having circuitry identical to the first current switch stage; another first current switch stage connected to the at least one first emitter follower, the another first current switch stage being connected between one of the current sources and the second current switch stage; another second current switch stage connected to the at least one second emitter follower, the another second current switch stage being connected between the other of the current sources and the first current switch stage, the another second current switch stage having circuitry identical to the another first current switch stage; and at least one load resistance member connected to the first current switch stage and the second current switch stage.
Claim 3
Dependent Claim
75 words
The circuit arrangement of claim 1, wherein the first input stage has two transistors with emitters and two diodes, the diodes being connected to the emitters of respective transistors, wherein the first input stage further comprises two resistance members, each connected to a respective diode, wherein the second input stage has circuitry identical to the first input stage, and wherein the resistance members of the first and second input stages have substantially identical resistance values.
Claim 4
Dependent Claim
50 words
The circuit arrangement of claim 2, wherein there are two first emitter followers and two second emitter followers, each including a transistor with an emitter and a resistance member connected to the emitter, and wherein the resistance members of the first and second emitter followers have substantially identical resistance values.
Claim 5
Dependent Claim
19 words
The circuit arrangement of claim 1, wherein the current through each of the current sources is substantially the same.
Claim 6
Dependent Claim
65 words
The circuit arrangement of claim 1, further comprising means, including a pair of operating voltage source poles, for receiving power and applying a potential difference between the pair of operating voltage source poles, the current sources being connected to one of the operating voltage source poles and the at least one load resistance member being connected to the other of the operating voltage source poles.
Claim 7
Dependent Claim
116 words
The circuit arrangement of claim 1, wherein the first current switch stage comprises four transistors having collectors, wherein the second current switch stage comprises four transistors having collectors, wherein there are two load resistance members having substantially identical resistance values, wherein one of the load resistance members is connected to the collectors of two of the transistors of the first current switch stage and to the collectors of two of the transistors of the second current switch stage, and wherein the other load resistance member is connected to the collectors of the other two transistors of the first current switch stage and to the collectors of the other two transistors of the second current switch stage.
Claim 8
Dependent Claim
67 words
The circuit arrangement of claim 1, wherein the first input stage includes two transistors and two diodes, wherein the second input stage has circuitry identical to the first input stage, wherein there are two first emitter followers, each connected to a respective diode of the first input stage, and wherein there are two second emitter followers, each connected to a respective diode of the second input stage.
Claim 9
Dependent Claim
16 words
The circuit arrangement of claim 1, wherein the arrangement is configured to E 2 CL technology.
Claim 10
Dependent Claim
305 words
A circuit arrangement for multiplying first and second input signals, comprising: a first input stage which receives the first input signal, the first input stage including at least one transistor and at least one diode; at least one first emitter follower connected to the at least one diode of the first input stage; a second input stage which receives the second input signal, the second input stage including at least one transistor and at least one diode; at least one second emitter follower connected to the at least one diode of the second input stage; a first predistortion stage connected to the at least one first emitter follower, the first predistortion stage including at least one feedback resistance member; a second predistortion stage connected to the at least one second emitter follower, the second predistortion stage including at least one feedback resistance member; a pair of current sources; a first current switch stage connected to the first predistortion stage; a second current switch stage connected to the second predistortion stage, the second current switch stage having circuitry identical to the first current switch stage; another first current switch stage connected to the at least one first emitter follower, the another first current switch stage including at least one feedback resistance member and being connected between one of the current sources and the second current switch stage; another second current switch stage connected to the at least one second emitter follower, the another second current switch stage including at least one feedback resistance member and being connected between the other of the current sources and the first current switch stage, the another second current switch stage having circuitry identical to the another first current switch stage; and at least one load resistance member connected to the first current switch stage and the second current switch stage.
Claim 11
Dependent Claim
305 words
A circuit arrangement for multiplying first and second input signals, comprising: a first input stage which receives the first input signal, the first input stage including at least one transistor and at least one diode; at least one first emitter follower connected to the at least one diode of the first input stage; a second input stage which receives the second input signal, the second input stage including at least one transistor and at least one diode; at least one second emitter follower connected to the at least one diode of the second input stage; a first predistortion stage connected to the at least one first emitter follower, the first predistortion stage including at least one feedback resistance member; a second predistortion stage connected to the at least one second emitter follower, the second predistortion stage including at least one feedback resistance member; a pair of current sources; a first current switch stage connected to the first predistortion stage; a second current switch stage connected to the second predistortion stage, the second current switch stage having circuitry identical to the first current switch stage; another first current switch stage connected to the at least one first emitter follower, the another first current switch stage including at least one feedback resistance member and being connected between one of the current sources and the second current switch stage; another second current switch stage connected to the at least one second emitter follower, the another second current switch stage including at least one feedback resistance member and being connected between the other of the current sources and the first current switch stage, the another second current switch stage having circuitry identical to the another first current switch stage; and at least one load resistance member connected to the first current switch stage and the second current switch stage.
Claim 12
Dependent Claim
65 words
The circuit arrangement of claim 9, further comprising means, including a pair of operating voltage source poles, for receiving power and applying a potential difference between the pair of operating voltage source poles, the current sources being connected to one of the operating voltage source poles and the at least one load resistance member being connected to the other of the operating voltage source poles.
Claim 13
Dependent Claim
79 words
The circuit arrangement of claim 10, wherein the first input stage additionally includes at least one resistance member connected between the base of the at least one transistor of the first input stage and said other of the operating voltage source poles, and wherein the second input stage additionally includes at least one resistance member connected between the base of the at least one transistor of the first input stage and said other of the operating voltage source poles.
Claim 14
Dependent Claim
123 words
The circuit arrangement of claim 9, wherein there are two first emitter followers, each including a transistor with an emitter, wherein there are two second emitter followers, each including a transistor with an emitter, wherein the first predistortion stage comprises two transistors with bases that are connected to the emitters of the first emitter followers, wherein the another first current switch stage comprises two transistors with bases that are connected to the emitters of the first emitter followers, wherein the second predistortion stage comprises two transistors with bases that are connected to the emitters of the second emitter followers, and wherein the another second current switch stage comprises two transistors with bases that are connected to the emitters of the second emitter followers.
Claim 15
Dependent Claim
105 words
The circuit arrangement of claim 9, wherein the first predistortion stage comprises two transistors with collectors, a resistance member, and two decoupling diodes, each decoupling diode of the first predistortion stage connecting the resistance member of the first predistortion stage with the collector of a respective one of the transistors of the first predistortion stage, and wherein the second predistortion stage comprises two transistors with collectors, a resistance member, and two decoupling diodes, each decoupling diode of the second predistortion stage connecting the resistance member of the second predistortion stage with the collector of a respective one of the transistors of the second predistortion stage.
Claim 16
Dependent Claim
43 words
The circuit arrangement of claim 9, further comprising another pair of current sources, one current source of the another pair being connected to the first predistortion stage and the other current source of the another pair being connected to the second predistortion stage.
Claim 17
Dependent Claim
160 words
The arrangement of claim 9, wherein the first predistortion stage comprises two transistors with collectors, wherein the first current switch stage comprises four transistors with bases, the bases of two of the transistors of the first current switch stage being connected to the collector of one of the transistors of the first predistortion stage and the bases of the other two transistors of the first current switch stage being connected to the collector of the other transistor of the first predistortion stage, wherein the second predistortion stage comprises two transistors with collectors, and wherein the second current switch stage comprises four transistors with bases, the bases of two of the transistors of the second current switch stage being connected to the collector of one of the transistors of the second predistortion stage and the bases of the other two transistors of the second current switch stage being connected to the collector of the other transistor of the second predistortion stage.
Claim 18
Dependent Claim
16 words
The circuit arrangement of claim 9, wherein the arrangement is configured in E 2 CL technology.
Claim 19
Dependent Claim
116 words
The circuit arrangement of claim 9, wherein the first current switch stage comprises four transistors having collectors, wherein the second current switch stage comprises four transistors having collectors, wherein there are two load resistance members, having substantially identical resistance values, wherein one of the load resistance members is connected to the collectors of two of the transistors of the first current switch stage and to the collectors of two of the transistors of the second current switch stage, and wherein the other load resistance member is connected to the collectors of the other two transistors of the first current switch stage and to the collectors of the other two transistors of the second current switch stage.
Claim 20
Dependent Claim
67 words
The circuit arrangement of claim 9, wherein the first input stage includes two transistors and two diodes, wherein the second input stage has circuitry identical to the first input stage, wherein there are two first emitter followers, each connected to a respective diode of the first input stage, and wherein there are two second emitter followers, each connected to a respective diode of the second input stage.
Claim 21
Dependent Claim
149 words
The circuit arrangement of claim 9, wherein the first predistortion stage has two feedback resistance members and further comprises two transistors with emitters, each feedback resistance member of the first predistortion stage being connected to the other feedback resistance member of the first predistortion stage and to the emitter of a respective transistor of the first predistortion stage, wherein the second predistortion stage has circuitry identical to the first predistortion stage, wherein the another first current switch stage has two feedback resistance members and further comprises two transistors with emitters, each feedback resistance member of the another first current switch stage being connected to the other feedback resistance member of the another first current switch stage and to the emitter of a respective transistor of the another first current switch stage, and wherein the second another current switch stage has circuitry identical to the another first current switch stage.
References Cited (Backward Citations)
US3649844A
Cited
US3838393A
Cited
US4041326A
Cited
US4408134A
Cited
US4924117A
Cited
US4718035A
Cited
US4831579A
Cited
US4810908A
Cited
US4900954A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-16 | 1995-12-16 | 1996-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-16 | 1999-12-16 | 2000-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-16 | 2003-12-16 | 2004-06-16 | $7700.00 | Window Closed / Lapsed |