US4718035A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic operation circuit having an exclusive-OR circuit
Assignee: Toshiba Corp
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Filing: 1985-05-15
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Granted: 1988-01-05
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Expires: 2005-05-15
Abstract
Abstract A logic operation circuit includes an exclusive-OR circuit for receiving first and second input signals, a carry output signal selection circuit for selectively generating a sum signal or an inverted signal thereof as a carry output signal in accordance with an output signal from the exclusive-OR circuit, and a carry output signal selection circuit for selectively generating a carry input signal or the first input signal as a sum signal in accordance with the output signal from the exclusive-OR circuit. The sum signal selection circuit has first and second differential amplifiers respectively driven by first and second output signals which are inverted to each other and received from the exclusive-OR circuit so as to generate the sum signal in accordance with the carry input signal, and the carry input signal selection circuit has third and fourth differential amplifiers respectively driven in accordance with the first and second output signals from the exclusive-OR circuit so as to generate carry output signals in accordance with the first input signal and carry input signal, respectively.
Inventors
- 👤 Hiroyuki Hara
- 👤 Yasuhiro Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:30
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4806
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
190 words
A logic operation circuit comprising: an exclusive-OR circuit for generating first and second output signals which are inverted to each other in accordance with first and second input signal; a sum signal selection circuit having first and second differential amplifier circuits which each include a plurality of transistors having emitter-collector paths connected between a power source terminal and the output terminals of said exclusive OR circuit and are driven by the first and second output signals from said exclusive-OR circuit to generate a sum signal in accordance with a carry input signal; and a carry output signal selection circuit including a third differential amplifier circuit driven by the first output signal from said exclusive-OR circuit to generate a carry output signal in accordance with the first input signal, and a fourth differential amplifier circuit driven in accordance with the second output signal from said exclusive-OR circuit to generate the carry output signal in accordance with the carry input signal, each of said third and fourth differential amplifier circuits including a plurality of transistors having emitter-collector paths connected between the power source terminal and the output terminals of said exclusive-OR circuit.
Claim 2
Dependent Claim
190 words
A logic operation circuit comprising: an exclusive-OR circuit for generating first and second output signals which are inverted to each other in accordance with first and second input signal; a sum signal selection circuit having first and second differential amplifier circuits which each include a plurality of transistors having emitter-collector paths connected between a power source terminal and the output terminals of said exclusive OR circuit and are driven by the first and second output signals from said exclusive-OR circuit to generate a sum signal in accordance with a carry input signal; and a carry output signal selection circuit including a third differential amplifier circuit driven by the first output signal from said exclusive-OR circuit to generate a carry output signal in accordance with the first input signal, and a fourth differential amplifier circuit driven in accordance with the second output signal from said exclusive-OR circuit to generate the carry output signal in accordance with the carry input signal, each of said third and fourth differential amplifier circuits including a plurality of transistors having emitter-collector paths connected between the power source terminal and the output terminals of said exclusive-OR circuit.
Claim 3
Dependent Claim
149 words
A circuit according to claim 1, wherein said exclusive-OR circuit comprises a fifth differential amplifier circuit driven by first constant current source to generate output signals which are inverted to each other from first and second output terminals thereof in accordance with the second input signal, a sixth differential amplifier circuit driven in accordance with the output signal from the first output terminal of said fifth differential amplifier circuit to generate first and second output signals from first and second output terminals thereof in accordance with the first input signal, and a seventh differential amplifier circuit driven in accordance with the output signal from the second output terminal of said fifth differential amplifier to generate first and second output signals from first and second output terminals thereof, respectively connected to the first and second output terminals of said sixth differential amplifier circuit, in accordance with the first input signal.
Claim 4
Dependent Claim
102 words
A circuit according to claim 2, wherein said sixth differential amplifier circuit comprises a first differential amplifier having first and second output terminals respectively connected to said first and second differential amplifier circuits and a second differential amplifier having first and second output terminals respectively connected to said third and fourth differential amplifier circuits, and said seventh differential amplifier circuit comprises a third differential amplifier having first and second output terminals respectively connected to said first and second differential amplifier circuits and a fourth differential amplifier having first and second output terminals respectively connected to said third and fourth differential amplifier circuits.
Claim 5
Dependent Claim
156 words
A circuit according to claim 2, wherein said fifth differential amplifier circuit includes first and second transistors having emitters commonly connected to said first constant current source, said first differential amplifier includes third and fourth transistors having emitters commonly connected to the collector of said first transistor and collectors respectively connected to said first and second differential amplifier circuits, said second differential amplifier includes fifth and sixth transistors having emitters commonly connected to the collector of said first transistor and collectors respectively connected to said third and fourth differential amplifier circuits, said third differential amplifier includes seventh and eighth transistors having emitters commonly connected to the collector of said second transistor and collectors respectively connected to said first and second differential amplifier circuits, and said fourth differential amplifier includes ninth and tenth transistors having emitters commonly connected to the collector of said second transistor and collectors respectively connected to said third and fourth differential amplifier circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |