US4621338A
Expired / Lapsed
US
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CMOS adder using exclusive OR and/or exclusive-NOR gates
Assignee: ITT Inc
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Filing: 1984-04-13
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Granted: 1986-11-04
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Expires: 2004-04-13
Abstract
Abstract To implement CMOS EXORs or EXNORs, four transistors are used which have one end of their channels tied to the gate output. The first and fourth transistors are one conductivity type, and the second and third transistors are of the other conductivity type. One of the inputs is split up into two sub-inputs to which one of the digital signals has to be applied in uninverted form and in inverted form, respectively. The other end of the channel of the fourth transistor is connected to the first sub-input in the case of the EXOR and to the second sub-input in the case of the EXNOR. The reverse is true for the channel of the third transistor, while the channels of the first and second transistors are connected to the second input. The latter is also connected to the gates of the third and fourth transistors. The gate of the first transistor is connected to the channel of the fourth transistor, while the gate of the second transistor is connected to the channel of the third transistor.
Inventors
- 👤 Arnold Uhlenhoff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:51
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/215; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3876
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
448 words
A CMOS full-adder stage having first inputs including two sub-inputs for a first signal to be added and a second input for a second signal to be added, and with a carry input for an uninverted carry signal, comprising: first and second exclusive-OR (EXOR) gate implemented using complementary metal-oxide-semiconductor technology (CMOS technology), each comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted two sub-inputs for one digital signal, respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said first sub-input; a second transistor having its gate connected to said second sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to said second sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input; the second channel terminal of said fourth transistor being connected to said first sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second channel terminal of said first transistor being connected to said second input, said stage further comprising: a clocked inverter; a static inverter; a transmission gate; wherein said first signal to be added is applied to said first sub-input and said second sub-input of said first EXOR in uninverted form and inverted form, respectively, and said second signal to be added is applied to said second input of said first EXOR; said first sub-input of said second EXOR is connected to said output of said first EXOR; said carry input is connected to said second input of said second EXOR and to the signal input of said clocked inverter; said output of said first EXOR is connected to the input of said static inverter, to the first clock input of said clocked inverter, and to the first clock input of said transmission gate; the second clock input of said transmission gate together with the second clock input of said clocked inverter being connected to the output of said static inverter; the output of said clocked inverter is the carry output; the output of said second EXOR being the sum output; and the switching path of said transmission gate is connected between said second sub-input and said carry output.
Claim 2
Dependent Claim
448 words
A CMOS full-adder stage having first inputs including two sub-inputs for a first signal to be added and a second input for a second signal to be added, and with a carry input for an uninverted carry signal, comprising: first and second exclusive-OR (EXOR) gate implemented using complementary metal-oxide-semiconductor technology (CMOS technology), each comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted two sub-inputs for one digital signal, respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said first sub-input; a second transistor having its gate connected to said second sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to said second sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input; the second channel terminal of said fourth transistor being connected to said first sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second channel terminal of said first transistor being connected to said second input, said stage further comprising: a clocked inverter; a static inverter; a transmission gate; wherein said first signal to be added is applied to said first sub-input and said second sub-input of said first EXOR in uninverted form and inverted form, respectively, and said second signal to be added is applied to said second input of said first EXOR; said first sub-input of said second EXOR is connected to said output of said first EXOR; said carry input is connected to said second input of said second EXOR and to the signal input of said clocked inverter; said output of said first EXOR is connected to the input of said static inverter, to the first clock input of said clocked inverter, and to the first clock input of said transmission gate; the second clock input of said transmission gate together with the second clock input of said clocked inverter being connected to the output of said static inverter; the output of said clocked inverter is the carry output; the output of said second EXOR being the sum output; and the switching path of said transmission gate is connected between said second sub-input and said carry output.
Claim 3
Dependent Claim
650 words
A CMOS full-adder stage with a first input consisting of two sub-inputs for a first signal to be added and a second input for a second signal to be added, and with a carry input for an inverted carry signal, comprising: a clocked inverter; a static inverter; a transmission gate; an exclusive OR (EXOR) gate; an exclusive NOR (EXNOR) gate; said EXOR gate comprising; a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted sub-inputs for one digital signal, respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said first sub-input; a second transistor having its gate connected to said second sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to second sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input the second channel terminal of said fourth transistor being connected to said first sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second channel terminal of said first transistor being connected to said second input; said EXNOR gate comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted sub-inputs for one digital signal respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said second sub-input; a second transistor having its gate connected to said first sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to said first sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input; the second channel terminal of said fourth transistor being connected to said second sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second terminal of said first transistor being connected to the second input, and wherein; said first signal to be added is applied to said first sub-input and said second sub-input of said EXOR in uninverted form and inverted form, respectively, and said second signal to be added is applied to said second input of said EXOR; said first sub-input of said EXNOR is connected to the output of said EXOR; said carry input is connected to said second input of said EXNOR and to the signal input of said clocked inverter; the output of said EXOR is connected to the input of said static inverter to a first clock input of said clocked inverter, and to a first clock input of said transmission gate; a second clock input of said transmission gate, together with a second clock input of said clocked inverter being connected to the output of said static inverter; the output of said clocked inverter is the output for an uninverted carry signal, and the output of said EXNOR is the sum output; and the switching path of said transmission gate is connected between the first sub-input or the second input of said EXOR and the carry output.
Claim 4
Dependent Claim
650 words
A CMOS full-adder stage with a first input consisting of two sub-inputs for a first signal to be added and a second input for a second signal to be added, and with a carry input for an inverted carry signal, comprising: a clocked inverter; a static inverter; a transmission gate; an exclusive OR (EXOR) gate; an exclusive NOR (EXNOR) gate; said EXOR gate comprising; a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted sub-inputs for one digital signal, respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said first sub-input; a second transistor having its gate connected to said second sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to second sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input the second channel terminal of said fourth transistor being connected to said first sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second channel terminal of said first transistor being connected to said second input; said EXNOR gate comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted sub-inputs for one digital signal respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said second sub-input; a second transistor having its gate connected to said first sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to said first sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input; the second channel terminal of said fourth transistor being connected to said second sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second terminal of said first transistor being connected to the second input, and wherein; said first signal to be added is applied to said first sub-input and said second sub-input of said EXOR in uninverted form and inverted form, respectively, and said second signal to be added is applied to said second input of said EXOR; said first sub-input of said EXNOR is connected to the output of said EXOR; said carry input is connected to said second input of said EXNOR and to the signal input of said clocked inverter; the output of said EXOR is connected to the input of said static inverter to a first clock input of said clocked inverter, and to a first clock input of said transmission gate; a second clock input of said transmission gate, together with a second clock input of said clocked inverter being connected to the output of said static inverter; the output of said clocked inverter is the output for an uninverted carry signal, and the output of said EXNOR is the sum output; and the switching path of said transmission gate is connected between the first sub-input or the second input of said EXOR and the carry output.
Claim 5
Dependent Claim
1160 words
A CMOS parallel adder comprising: a plurality of full adder stages each having its carry output coupled to the carry input of the next stage; alternate ones of said plurality of stages being of a first type and intermediate ones of said plurality of stages being of a second type; each said first type stage being a CMOS full-adder stage having first inputs including two sub-inputs for a first signal to be added and a second input for a second signal to be added, and with a carry input for an uninverted carry signal, comprising: first and second exclusive-OR (EXOR) gate implemented using complementary metal-oxide-semiconductor technology (CMOS technology), each comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted two sub-inputs for one digital signal, respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said first sub-input; a second transistor having its gate connected to said second sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to said second sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input; the second channel terminal of said fourth transistor being connected to said first sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second channel terminal of said first transistor being connected to said second input said stage further comprising: a clocked inverter; a static inverter; a transmission gate; wherein said first signal to be added is applied to said first sub-input and said second sub-input of said first EXOR in uninverted form and inverted form, respectively, and said second signal to be added is applied to said second input of said first EXOR; said first sub-input of said second EXOR is connected to said output of said first EXOR; said carry input is connected to said second input of said second EXOR and to the signal input of said clocked inverter; said output of said first EXOR is connected to the input of said static inverter, to the first clock input of said clocked inverter, and to the first clock input of said transmission gate; the second clock input of said transmission gate together with the second clock input of said clocked inverter being connected to the output of said static inverter; the output of said clocked inverter is the carry output; the output of said second EXOR being the sum output; and the switching path of said transmission gate is connected between said second sub-input and said carry output; each said second type stage being a CMOS full-adder stage with a first input consisting of two sub-inputs for a first signal to be added and a second input for a second signal to be added, and with a carry input for an inverted carry signal, comprising: a clocked inverter; a static inverter; a transmission gate; an exclusive OR (EXOR) gate; an exclusive NOR (EXNOR) gate; said EXOR gate comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted sub-inputs for one digital signal, respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said first sub-input; a second transistor having its gate connected to said second sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to second sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input the second channel terminal of said fourth transistor being connected to said first sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second channel terminal of said first transistor being connected to said second input; said EXNOR gate comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted sub-inputs for one digital signal respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said second sub-input; a second transistor having its gate connected to said first sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to said first sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input; the second channel terminal of said fourth transistor being connected to said second sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second terminal of said first transistor being connected to the second input, and wherein; said first signal to be added is applied to said first sub-input and said second sub-input of said EXOR in uninverted form and inverted form, respectively, and said second signal to be added is applied to said second input of said EXOR; said first sub-input of said EXNOR is connected to the output of said EXOR; said carry input is connected to said second input of said EXNOR and to the signal input of said clocked inverter; the output of said EXOR is connected to the input of said static inverter to a first clock input of said clocked inverter, and to a first clock input of said transmission gate; a second clock input of said transmission gate, together with a second clock input of said clocked inverter being connected to the output of said static inverter; the output of said clocked inverter is the output for an uninverted carry signal, and the output of said EXNOR is the sum output; and the switching path of said transmission gate is connected between the first sub-input or the second input of said EXOR and the carry output.
Claim 6
Dependent Claim
1160 words
A CMOS parallel adder comprising: a plurality of full adder stages each having its carry output coupled to the carry input of the next stage; alternate ones of said plurality of stages being of a first type and intermediate ones of said plurality of stages being of a second type; each said first type stage being a CMOS full-adder stage having first inputs including two sub-inputs for a first signal to be added and a second input for a second signal to be added, and with a carry input for an uninverted carry signal, comprising: first and second exclusive-OR (EXOR) gate implemented using complementary metal-oxide-semiconductor technology (CMOS technology), each comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted two sub-inputs for one digital signal, respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said first sub-input; a second transistor having its gate connected to said second sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to said second sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input; the second channel terminal of said fourth transistor being connected to said first sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second channel terminal of said first transistor being connected to said second input said stage further comprising: a clocked inverter; a static inverter; a transmission gate; wherein said first signal to be added is applied to said first sub-input and said second sub-input of said first EXOR in uninverted form and inverted form, respectively, and said second signal to be added is applied to said second input of said first EXOR; said first sub-input of said second EXOR is connected to said output of said first EXOR; said carry input is connected to said second input of said second EXOR and to the signal input of said clocked inverter; said output of said first EXOR is connected to the input of said static inverter, to the first clock input of said clocked inverter, and to the first clock input of said transmission gate; the second clock input of said transmission gate together with the second clock input of said clocked inverter being connected to the output of said static inverter; the output of said clocked inverter is the carry output; the output of said second EXOR being the sum output; and the switching path of said transmission gate is connected between said second sub-input and said carry output; each said second type stage being a CMOS full-adder stage with a first input consisting of two sub-inputs for a first signal to be added and a second input for a second signal to be added, and with a carry input for an inverted carry signal, comprising: a clocked inverter; a static inverter; a transmission gate; an exclusive OR (EXOR) gate; an exclusive NOR (EXNOR) gate; said EXOR gate comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted sub-inputs for one digital signal, respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said first sub-input; a second transistor having its gate connected to said second sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to second sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input the second channel terminal of said fourth transistor being connected to said first sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second channel terminal of said first transistor being connected to said second input; said EXNOR gate comprising: a first sub-input of a first input and an associated second sub-input for receiving inverted and uninverted sub-inputs for one digital signal respectively; a second input for receiving a second digital signal in uninverted form; a first transistor of one conductivity type having its gate connected to said second sub-input; a second transistor having its gate connected to said first sub-input; a third transistor of a second conductivity type having its gate connected to said second input; a fourth transistor of said one conductivity type; a gate output coupled to one channel terminal of each of said first, second, third and fourth transistors; a second channel terminal of said second transistor being connected to said second input; a second channel terminal of said third transistor being connected to said first sub-input; said second transistor being of said second conductivity type; the gate of said fourth transistor being connected to said second input; the second channel terminal of said fourth transistor being connected to said second sub-input; the gate of said first transistor being connected to the second channel terminal of said fourth transistor; and the second terminal of said first transistor being connected to the second input, and wherein; said first signal to be added is applied to said first sub-input and said second sub-input of said EXOR in uninverted form and inverted form, respectively, and said second signal to be added is applied to said second input of said EXOR; said first sub-input of said EXNOR is connected to the output of said EXOR; said carry input is connected to said second input of said EXNOR and to the signal input of said clocked inverter; the output of said EXOR is connected to the input of said static inverter to a first clock input of said clocked inverter, and to a first clock input of said transmission gate; a second clock input of said transmission gate, together with a second clock input of said clocked inverter being connected to the output of said static inverter; the output of said clocked inverter is the output for an uninverted carry signal, and the output of said EXNOR is the sum output; and the switching path of said transmission gate is connected between the first sub-input or the second input of said EXOR and the carry output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-03 | 1990-05-05 | 1990-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-03 | 1994-05-05 | 1994-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-03 | 1998-05-05 | 1998-11-04 | $7700.00 | Window Closed / Lapsed |