US4041326A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed complementary output exclusive OR/NOR circuit
Assignee: Fairchild Semiconductor Corp
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Filing: 1977-02-22
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Granted: 1977-08-09
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Expires: 1997-02-22
Abstract
Abstract A very high-speed exclusive OR/NOR circuit in which output function and its complement are propagated simultaneously. Developed particularly for use in integrated circuit applications, the basis circuit uses six NPN transistors in a tree configuration to select one of four mutually exclusive conductive paths which correspond to the four states of the truth table of a two-variable exclusive OR/NOR function.
Inventors
- 👤 Barry J. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/212
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
262 words
A high-speed exclusive OR/NOR circuit comprising: a plurality of NPN transistor pairs arranged in a tree configuration of at least two levels, the first of said pairs being at a first level and having the emitters of each transistor in said pair being connected directly to ground reference, the collector of each transistor in said first pair being connected to the interconnected emitters of a second transistor pair and a third transistor pair in the second level; first input signal means coupled to said first transistor pair for selectively enabling the first and disabling the second transistor in said first pair; second input signal means coupled to said second and said third transistor pair for selectively enabling the first and disabling the second transistor in each of said second and said third pairs; first current source circuitry including a first resistance coupled between a source of D.C. potential and a first conductor intercoupling the collector of the transistor in said second pair enabled by said second input signal means with the transistor in said third pair disabled by said second input signal means; second current source circuitry including a second resistance coupled between said source of D.C. potential and a second conductor intercoupling the collector of the transistor in said third pair enabled by said second input signal means with the transistor in said second pair disabled by said input signal means; and first output means coupled to said first conductor for signalling current flow from said source of D.C. potential through said first resistance and through enabled transistors to ground potential.
Claim 2
Dependent Claim
262 words
A high-speed exclusive OR/NOR circuit comprising: a plurality of NPN transistor pairs arranged in a tree configuration of at least two levels, the first of said pairs being at a first level and having the emitters of each transistor in said pair being connected directly to ground reference, the collector of each transistor in said first pair being connected to the interconnected emitters of a second transistor pair and a third transistor pair in the second level; first input signal means coupled to said first transistor pair for selectively enabling the first and disabling the second transistor in said first pair; second input signal means coupled to said second and said third transistor pair for selectively enabling the first and disabling the second transistor in each of said second and said third pairs; first current source circuitry including a first resistance coupled between a source of D.C. potential and a first conductor intercoupling the collector of the transistor in said second pair enabled by said second input signal means with the transistor in said third pair disabled by said second input signal means; second current source circuitry including a second resistance coupled between said source of D.C. potential and a second conductor intercoupling the collector of the transistor in said third pair enabled by said second input signal means with the transistor in said second pair disabled by said input signal means; and first output means coupled to said first conductor for signalling current flow from said source of D.C. potential through said first resistance and through enabled transistors to ground potential.
Claim 3
Dependent Claim
38 words
The circuit claimed in claim 1 further including second output means coupled to said second conductor for signalling current flow from said source of D.C. potential through said second resistance and through enabled transistors to said ground reference.
Claim 4
Dependent Claim
19 words
The circuit claimed in claim 1 in which the transistors in said plurality of transistor pairs are Schottky clamped.
Claim 5
Dependent Claim
89 words
The circuit claimed in claim 3 wherein said first input signal means includes an input NPN transistor having an emitter and collector respectively coupled through resistances to said ground reference and to said D.C. potential source, and respectively coupled to the bases of said first and second transistors in said first transistor pair, said input NPN transistor being rendered conductive and non-conductive by the application of high and low input signals respectively whereby said first and second transistors in said first transistor pair are respectively rendered conductive and non-conductive.
Claim 6
Dependent Claim
128 words
The circuit claimed in claim 4 wherein said second input signal means includes: a second input NPN transistor biased between said D.C. potential source and ground reference for conduction and non-conduction by the respective presence and absence of an applied input signal, the emitter of said second input transistor being coupled to the bases of first and second transistors in said second and third transistor pairs; and a multiple-emitter NPN transistor having first and second emitters coupled for conduction respectively through said first and second transistors in said first transistor pair, and a collector coupled to the bases of the first and second transistors in said third and second transistor pairs; the base of said multiple-emitter transistor being coupled to the emitter of said second input NPN transistor.
Claim 7
Dependent Claim
74 words
The circuit claimed in claim 3 further including fourth and fifth transistor pairs interposed between said second and third transistor pairs and said first and second current source circuitry, respectively, each transistor in said fourth and fifth pairs having a plurality of emitters, the first and second emitters of the first and second transistors in each of said pairs being interconnected and to an emitter of a transistor in said second and third pair.
Claim 8
Dependent Claim
82 words
The circuit claimed in claim 6 further including third input signal means coupled to said fourth and fifth transistor pairs for selectively enabling the first and disabling the second transistor in each of said pairs, whereby the application of first, second, and third input signals will enable one transistor in said first, said second and third, and said fourth and fifth pairs to provide a mutually exclusive current path from said D.C. potential source and through said enabled transistors to ground reference.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-08 | 1981-02-07 | 1981-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-08 | 1985-02-07 | 1985-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-08 | 1989-02-07 | 1989-08-09 | $7700.00 | Window Closed / Lapsed |