Patent US5117488A successfully refreshed from Google Patents.
US5117488A
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Microprogram controlled microprocessor having a selectively expandable instruction code length including independent description of operand addressing and a type of operation for an operand by single instruction in a common coding scheme
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1988-11-01
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Granted: 1992-05-26
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Expires: 2008-11-01
Abstract
Abstract In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.
Inventors
- 👤 Kouki Noguchi
- 👤 Fumio Tsuchiya
- 👤 Takashi Tsukamoto
- 👤 Shigeki Masumura
- 👤 Hideo Nakamura
- 👤 Shiro Baba
- 👤 Yoshimune Hagiwara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/30; G06F9/3017; G06F9/30178; G06F9/26; G06F9/261; G06F9/30145; G06F9/30156
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
177 words
A microprogram controlled microprocessor having an instruction for selectively independently setting an operand addressing mode and a type of operation for an operand in one instruction, wherein said instruction outputted from an instruction register is selectively expandable by a unit of predetermined bit length, a first portion of said predetermined bit length code comprising a first instruction code designating said operand addressing, a second portion of said predetermined bit length code comprising a second instruction code designating an operation mode for said operand, said first instruction code and said second instruction code having common coding schemes, comprising: a combinational logic circuit means for sequentially receiving said first instruction code and then said second instruction code in units of said predetermined bit length and decoding each of the codes by compressing into a shorter bit length with respect to said predetermined bit length thereby comprising an output signal; and means for generating an address of a microprogram by merging the output signal of said combinational logic circuit and at least a portion of bit information of the microprogram.
Claim 2
Dependent Claim
177 words
A microprogram controlled microprocessor having an instruction for selectively independently setting an operand addressing mode and a type of operation for an operand in one instruction, wherein said instruction outputted from an instruction register is selectively expandable by a unit of predetermined bit length, a first portion of said predetermined bit length code comprising a first instruction code designating said operand addressing, a second portion of said predetermined bit length code comprising a second instruction code designating an operation mode for said operand, said first instruction code and said second instruction code having common coding schemes, comprising: a combinational logic circuit means for sequentially receiving said first instruction code and then said second instruction code in units of said predetermined bit length and decoding each of the codes by compressing into a shorter bit length with respect to said predetermined bit length thereby comprising an output signal; and means for generating an address of a microprogram by merging the output signal of said combinational logic circuit and at least a portion of bit information of the microprogram.
Claim 3
Dependent Claim
16 words
A microprogram controlled microprocessor according to claim 1 wherein said predetermined bit length is 8-bit length.
Claim 4
Dependent Claim
34 words
The microprogram controlled microprocessor according to claim 1 wherein the instruction has a form of instruction code including means for designating the addressing mode and the operation simultaneously by said predetermined number of bits.
Claim 5
Dependent Claim
43 words
The microprogram controlled microprocessor according to claim 1 wherein a start address of a microprogram subroutine is generated by merging the output signal of said combinational logic circuit and decode mode information of said microprogram outputted from a microprogram storage storing a microprogram.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |