US5116777A
Expired / Lapsed
US
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Method for fabricating semiconductor devices by use of an N+ buried layer for complete isolation
Assignee: STMicroelectronics lnc USA
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Filing: 1990-04-30
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Granted: 1992-05-26
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Expires: 2010-04-30
Abstract
Abstract An N + buried layer is formed under all the N-channel devices in the memory array of an integrated circuit device. The N + buried layer can also be formed under N-channel input/output devices. The N + buried layers include contacts to the power supply. Such a device layout provides for complete isolation of the memory array from the remainder of the circuitry. The isolation of the N-channel input/output devices also provides for enhanced immunity to input/output noise.
Inventors
- 👤 Tsiu C. Chan
- 👤 Mehdi Zamanian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:49
CPC Classifications
H; H10; H10W; H10W15/00; H10B; H10B12/00; H10B12/10; H10D; H10D84/00; H10D84/40; H10D84/401; H10W15/01; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
80 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming an N-type buried layer in a substrate; forming an epitaxial silicon layer above said buried layer; forming a plurality of P-type regions in said epitaxial layer; forming a plurality of contacts to said N-type buried layer through said epitaxial layer wherein the plurality of contacts are spaced at regular intervals throughout the memory array; and forming an array of N-channel field effect devices in said P-type regions.
Claim 2
Independent Claim
80 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming an N-type buried layer in a substrate; forming an epitaxial silicon layer above said buried layer; forming a plurality of P-type regions in said epitaxial layer; forming a plurality of contacts to said N-type buried layer through said epitaxial layer wherein the plurality of contacts are spaced at regular intervals throughout the memory array; and forming an array of N-channel field effect devices in said P-type regions.
Claim 3
Dependent Claim
15 words
The method of claim 1, wherein the contacts comprise N-type diffusions through the epitaxial layer.
Claim 4
Dependent Claim
24 words
The method of claim 1, wherein at least one additional contact to the N-type buried layer forms a continuous structure around a memory array.
Claim 5
Dependent Claim
55 words
The method of claim 1, further comprising the steps of: forming N-type buried layers in locations wherein input/output N-channel devices are to be formed; forming input/output P-type regions over such N-type buried layers; forming contacts to the input/output buried layers through the input/output P-type regions; and forming N-channel input/output devices in the input/output P-type regions.
Claim 6
Independent Claim
86 words
A method for fabricating semiconductor integrated devices, comprising the steps of: forming an N-type buried layer and a P-type buried layer in a substrate; forming an epitaxial silicon layer above said buried layers; forming a plurality of P-type regions in said epitaxial layer at least one over said N-type buried layer; forming at least one contact to said N-type buried layer through said epitaxial layer; and forming at least one N-channel field effect device in said at least one P-type region over said N-type buried layer.
Claim 7
Independent Claim
86 words
A method for fabricating semiconductor integrated devices, comprising the steps of: forming an N-type buried layer and a P-type buried layer in a substrate; forming an epitaxial silicon layer above said buried layers; forming a plurality of P-type regions in said epitaxial layer at least one over said N-type buried layer; forming at least one contact to said N-type buried layer through said epitaxial layer; and forming at least one N-channel field effect device in said at least one P-type region over said N-type buried layer.
Claim 8
Dependent Claim
18 words
The method of claim 5, wherein the at least one contact comprises N-type diffusions through the epitaxial layer.
Claim 9
Dependent Claim
27 words
The method of claim 5, further comprising the step of: forming N-type buried collector layers under the epitaxial layer in which NPN transistors are to be formed.
Claim 10
Dependent Claim
33 words
The method of claim 7, further comprising the step of: when the at least one contact is formed to the N-type buried layer, also forming N-type diffusions to contact the buried collector layers.
Claim 11
Dependent Claim
24 words
The method of claim 5, wherein the at least one contact to the N-type buried layer forms a continuous structure around a memory array.
Claim 12
Dependent Claim
55 words
The method of claim 5, further comprising the steps of: forming N-type buried layers in locations wherein input/output N-channel devices are to be formed; forming input/output P-type regions over such N-type buried layers; forming contacts to the input/output buried layers through the input/output P-type regions; and forming N-channel input/output devices in the input/output P-type regions.
Claim 13
Independent Claim
72 words
A method for fabricating semiconductor integrated devices, comprising the steps of: forming an N-type buried layer in a substrate; forming an epitaxial silicon layer above said buried layer; forming a plurality of P-type regions in said epitaxial layer; forming a contact to said buried layer through said epitaxial layer, said contact forming a continuous structure around a memory array, and forming a plurality of N-channel field effect devices in said P-type regions.
Claim 14
Independent Claim
72 words
A method for fabricating semiconductor integrated devices, comprising the steps of: forming an N-type buried layer in a substrate; forming an epitaxial silicon layer above said buried layer; forming a plurality of P-type regions in said epitaxial layer; forming a contact to said buried layer through said epitaxial layer, said contact forming a continuous structure around a memory array, and forming a plurality of N-channel field effect devices in said P-type regions.
Claim 15
Dependent Claim
55 words
The method of claim 11, further comprising the steps of: forming N-type buried layers in locations wherein input/output N-channel devices are to be formed; forming input/output P-type regions over said N-type buried layers; forming contacts to the input/output buried layers through the input/output P-type regions; and forming N-channel input/output devices in the input/output P-type regions.
Claim 16
Dependent Claim
15 words
The method of claim 11 wherein the contacts comprise N-type diffusions through said epitaxial layer.
Claim 17
Dependent Claim
27 words
The method of claim 11, further comprising the step of: forming N-type buried collector layers under the epitaxial layer in which NPN transistors are to be formed.
Claim 18
Dependent Claim
32 words
The method of claim 14, further comprising the step of: when the plurality of contacts are formed to said buried collector layers, also forming N-type diffusions to contact the buried collector layers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |