US4892836A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices
Assignee: STMicroelectronics SRL
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Filing: 1987-03-23
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Granted: 1990-01-09
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Expires: 2007-03-23
Abstract
Abstract This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.
Inventors
- 👤 Antonio Andreini
- 👤 Claudio Contiero
- 👤 Paola Galbiati
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:01
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/0142; H10D84/0163; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/837; H10D84/839; H10D84/85; H10D84/856; H10P; H10P76/00; H10P76/40; H10D84/8311; H10D84/8312; H10D84/83138
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
96 words
In a method for manufacturing semiconductor integrated circuits comprising a CMOS device and a high voltage electronic device, the CMOS device including an N-channel transistor having a P-well region and said high voltage electronic device having a border region in which an extended border portion is diffused to withstand the high voltage, the only step of simultaneously implanting the P-well region and at least one part of said extended border portion at said border region, by implanting impurities having a P-type conductivity and a preset concentration with a protective mask obtained through a single photolithographic step.
Claim 2
Dependent Claim
96 words
In a method for manufacturing semiconductor integrated circuits comprising a CMOS device and a high voltage electronic device, the CMOS device including an N-channel transistor having a P-well region and said high voltage electronic device having a border region in which an extended border portion is diffused to withstand the high voltage, the only step of simultaneously implanting the P-well region and at least one part of said extended border portion at said border region, by implanting impurities having a P-type conductivity and a preset concentration with a protective mask obtained through a single photolithographic step.
Claim 3
Dependent Claim
116 words
In a method for manufacturing semiconductor integrated circuits comprising a CMOS device and a high voltage electronic device, with the CMOS device including an N-channel transistor having a P-well region being surrounded by a CMOS isolation region, said CMOS device having a first extended border portion and said high voltage electronic device having a border region in which a further extended border portion is diffused, the only step of simultaneously implanting the P-well region, at least one part of said first extended border portion and at least one part of said further extended border portion, by implanting impurities having a P-type conductivity and a first concentration with a protective mask obtained through a single photolithographic step.
Claim 4
Dependent Claim
116 words
In a method for manufacturing semiconductor integrated circuits comprising a CMOS device and a high voltage electronic device, with the CMOS device including an N-channel transistor having a P-well region being surrounded by a CMOS isolation region, said CMOS device having a first extended border portion and said high voltage electronic device having a border region in which a further extended border portion is diffused, the only step of simultaneously implanting the P-well region, at least one part of said first extended border portion and at least one part of said further extended border portion, by implanting impurities having a P-type conductivity and a first concentration with a protective mask obtained through a single photolithographic step.
Claim 5
Dependent Claim
12 words
A method according to claim 1, wherein said impurities are boron atoms.
Claim 6
Dependent Claim
185 words
In a method for manufacturing semiconductor integrated circuits comprising a CMOS device and a high voltage electronic device, with the CMOS device including an N-channel transistor having a P-well region being surrounded by a CMOS isolation region, said CMOS device having a first extended border portion being diffused adjacent to said CMOS isolation region and said high voltage electronic device having a border region in which a further extended border portion is diffused, the first step of simultaneously implanting the P-well region, a first part of said first extended border portion and a first part of said further extended border portion, by implanting impurities having a P-type conductivity and a first concentration with a first protective mask obtained through a single photolithographic step, the second step of implanting said isolation region by implanting impurities having said P-type conductivity and a second concentration with a second protective mask and the further step of implanting at least one second part of said first extended border portion, by implanting impurities having said P-type conductivity and a further concentration lower than said first concentration with a further protective mask.
Claim 7
Dependent Claim
185 words
In a method for manufacturing semiconductor integrated circuits comprising a CMOS device and a high voltage electronic device, with the CMOS device including an N-channel transistor having a P-well region being surrounded by a CMOS isolation region, said CMOS device having a first extended border portion being diffused adjacent to said CMOS isolation region and said high voltage electronic device having a border region in which a further extended border portion is diffused, the first step of simultaneously implanting the P-well region, a first part of said first extended border portion and a first part of said further extended border portion, by implanting impurities having a P-type conductivity and a first concentration with a first protective mask obtained through a single photolithographic step, the second step of implanting said isolation region by implanting impurities having said P-type conductivity and a second concentration with a second protective mask and the further step of implanting at least one second part of said first extended border portion, by implanting impurities having said P-type conductivity and a further concentration lower than said first concentration with a further protective mask.
Claim 8
Dependent Claim
12 words
A method according to claim 4, wherein said impurities are boron ions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-08 | 1993-07-10 | 1994-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-08 | 1997-07-10 | 1998-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-08 | 2001-07-10 | 2002-01-09 | $7700.00 | Window Closed / Lapsed |