Method of producing semiconductor memory device with buried barrier layer

Claim 1

A method producing a semiconductor memory device, comprising the steps of: (1) preparing a semiconductor substrate having a principal surface, said substrate having a memory cell region of a first conductivity type in which memory cells are to be formed and a peripheral circuit region in which a peripheral circuit is to be formed; (2) forming a first insulator film on said principal surface of said substrate in said memory cell region and said peripheral circuit region; (3) selectively forming a second insulator film having oxidation resistance on said first insulator film so that said second insulator film covers a first active region in said memory cell region and a second active region in said peripheral circuit region; (4) selectively introducing first impurities of the first conductivity type into said principal surface of said peripheral circuit region, without introducing said first impurities in the memory cell region, by using the second insulator film formed on said peripheral circuit region as a mask in order to form a first channel stopper region in said peripheral circuit region without introducing the first impurities in the memory cell region; (5) after the step of selectively introducing said first impurities, selectively forming third and fourth insulator films on the principal surface of said substrate in said memory cell region and said peripheral circuit region respectively by using said second insulator film as an oxidation resistance mask, said third and fourth insulator films being thicker than said first insulator film; (6) removing said second insulator film from the upper surface of said first insulator film; (7) after the step of selectively forming the third and fourth insulator films, introducing second impurities of the first conductivity type all over said memory cell region, through at least said third insulator film, thereby to form a second channel stopper region of the first conductivity type, in said memory cell region, extending under the third insulator film, and a barrier region of the first conductivity type extending under a first active region, said barrier region having a higher impurity concentration than that of said memory cell region; (8) forming a MISFET included in each of said memory cells in said first active region within said memory cell region; and (9) forming MISFETs in said second active region within said peripheral circuit region, said MISFETs being included in said peripheral circuit.

Claim 2

A method producing a semiconductor memory device, comprising the steps of: (1) preparing a semiconductor substrate having a principal surface, said substrate having a memory cell region of a first conductivity type in which memory cells are to be formed and a peripheral circuit region in which a peripheral circuit is to be formed; (2) forming a first insulator film on said principal surface of said substrate in said memory cell region and said peripheral circuit region; (3) selectively forming a second insulator film having oxidation resistance on said first insulator film so that said second insulator film covers a first active region in said memory cell region and a second active region in said peripheral circuit region; (4) selectively introducing first impurities of the first conductivity type into said principal surface of said peripheral circuit region, without introducing said first impurities in the memory cell region, by using the second insulator film formed on said peripheral circuit region as a mask in order to form a first channel stopper region in said peripheral circuit region without introducing the first impurities in the memory cell region; (5) after the step of selectively introducing said first impurities, selectively forming third and fourth insulator films on the principal surface of said substrate in said memory cell region and said peripheral circuit region respectively by using said second insulator film as an oxidation resistance mask, said third and fourth insulator films being thicker than said first insulator film; (6) removing said second insulator film from the upper surface of said first insulator film; (7) after the step of selectively forming the third and fourth insulator films, introducing second impurities of the first conductivity type all over said memory cell region, through at least said third insulator film, thereby to form a second channel stopper region of the first conductivity type, in said memory cell region, extending under the third insulator film, and a barrier region of the first conductivity type extending under a first active region, said barrier region having a higher impurity concentration than that of said memory cell region; (8) forming a MISFET included in each of said memory cells in said first active region within said memory cell region; and (9) forming MISFETs in said second active region within said peripheral circuit region, said MISFETs being included in said peripheral circuit.

Claim 12

A method of producing a semiconductor memory device, comprising the steps of: preparing a semiconductor substrate having a principal surface, said substrate having a memory cell region in which a plurality of memory cells are to be formed and a peripheral circuit region in which a peripheral circuit is to be formed, wherein said memory cell region includes first active regions of a first conductivity type and a first isolation region for isolating said first active regions from each other, wherein said peripheral circuit region includes second and third active regions and a second isolation region for isolating said second and third active regions from each other, the second active region having the first conductivity type, the third active region having a second conductivity type opposite to the first conductivity type; selectively introducing first impurities of the first conductivity type into the principal surface on said peripheral circuit region without introducing said first impurities into the memory cell region, in order to form a first channel stopper region in said second isolation region; after the step of selectively introducing said first impurities, selectively forming a first insulator film on the principal surface of said substrate at said first isolation region in said memory cell region and a second insulator film on the principal surface of said substrate in said peripheral circuit region, respectively, said first channel stopper region being disposed under said second insulator film; after the step of selectively forming the first and second insulator films, implanting second impurities of the first conductivity type into said memory cell region, through at least said first insulator film, to thereby form a second channel stopper region of the first conductivity type under said first insulator film and an impurity-introduced region of the first conductivity type under said first active regions, said impurity-introduced region being integrally formed with said second channel stopper region in said substrate and having a higher concentration than that of said first active regions; and forming first MISFETs of said memory cells in said first active regions, and forming second and third MISFETs of said peripheral circuit in said second and third active regions, respectively.

Claim 13

A method of producing a semiconductor memory device, comprising the steps of: preparing a semiconductor substrate having a principal surface, said substrate having a memory cell region in which a plurality of memory cells are to be formed and a peripheral circuit region in which a peripheral circuit is to be formed, wherein said memory cell region includes first active regions of a first conductivity type and a first isolation region for isolating said first active regions from each other, wherein said peripheral circuit region includes second and third active regions and a second isolation region for isolating said second and third active regions from each other, the second active region having the first conductivity type, the third active region having a second conductivity type opposite to the first conductivity type; selectively introducing first impurities of the first conductivity type into the principal surface on said peripheral circuit region without introducing said first impurities into the memory cell region, in order to form a first channel stopper region in said second isolation region; after the step of selectively introducing said first impurities, selectively forming a first insulator film on the principal surface of said substrate at said first isolation region in said memory cell region and a second insulator film on the principal surface of said substrate in said peripheral circuit region, respectively, said first channel stopper region being disposed under said second insulator film; after the step of selectively forming the first and second insulator films, implanting second impurities of the first conductivity type into said memory cell region, through at least said first insulator film, to thereby form a second channel stopper region of the first conductivity type under said first insulator film and an impurity-introduced region of the first conductivity type under said first active regions, said impurity-introduced region being integrally formed with said second channel stopper region in said substrate and having a higher concentration than that of said first active regions; and forming first MISFETs of said memory cells in said first active regions, and forming second and third MISFETs of said peripheral circuit in said second and third active regions, respectively.

Claim 24

A method of manufacturing a semiconductor memory device, comprising the steps of: (a) preparing a semiconductor substrate having a main surface, said substrate having a memory cell region in which a plurality of memory cells are to be formed, and having a peripheral circuit region in which a peripheral circuit is to be formed, wherein said memory cell region includes first active regions of a first conductivity type and a first isolation region for isolating said first active regions from each other, wherein said peripheral circuit region includes second active regions and a second isolation region for isolating said second active regions each other; (b) selectively forming a mask film on said main surface of said substrate so that said mask film covers first active regions and said first isolation region in said memory cell region and said second active regions in said peripheral circuit region; (c) selectively introducing first impurities of said first conductivity type into said main surface of said substrate by using mask film as a mask, to form a first channel stopper region of said first conductivity type at said second isolation region in said peripheral circuit region; (d) after the step (c), selectively forming an isolation oxide film on said main surface of said substrate so that said isolation oxide film is disposed at said first and second isolation regions; (e) after the step (d), introducing second impurities of said first conductivity type into said memory cell region of said substrate, through at least said isolation oxide film, to form a second channel stopper region of said first conductivity type under said isolation oxide film and a barrier region under said first active regions, said barrier region being integrally formed with said second channel stopper region in said substrate and having a higher impurity concentration than that of said first active regions of said memory cell region.

Claim 25

A method of manufacturing a semiconductor memory device, comprising the steps of: (a) preparing a semiconductor substrate having a main surface, said substrate having a memory cell region in which a plurality of memory cells are to be formed, and having a peripheral circuit region in which a peripheral circuit is to be formed, wherein said memory cell region includes first active regions of a first conductivity type and a first isolation region for isolating said first active regions from each other, wherein said peripheral circuit region includes second active regions and a second isolation region for isolating said second active regions each other; (b) selectively forming a mask film on said main surface of said substrate so that said mask film covers first active regions and said first isolation region in said memory cell region and said second active regions in said peripheral circuit region; (c) selectively introducing first impurities of said first conductivity type into said main surface of said substrate by using mask film as a mask, to form a first channel stopper region of said first conductivity type at said second isolation region in said peripheral circuit region; (d) after the step (c), selectively forming an isolation oxide film on said main surface of said substrate so that said isolation oxide film is disposed at said first and second isolation regions; (e) after the step (d), introducing second impurities of said first conductivity type into said memory cell region of said substrate, through at least said isolation oxide film, to form a second channel stopper region of said first conductivity type under said isolation oxide film and a barrier region under said first active regions, said barrier region being integrally formed with said second channel stopper region in said substrate and having a higher impurity concentration than that of said first active regions of said memory cell region.