Method for manufacturing a junction field effect transistor

Claim 1

A method for manufacturing a heterojunction type field effect transistor comprising: a first epitaxy growth process for growing a N type GaInAs(P) channel layer, a N type InP layer and a GaInAs(P) layer on a semi-insulating substrate, a selective etching process of the GaInAs(P) layer and the N type InP layer for selectively anisotropically etching only the GaInAs(P) layer by using a selective etching solution, and selectively etching the N type InP layer additionally, after lithographically forming an etching mask of photoresist, a second epitaxy growth process for growing a P type InP layer for a PN junction after removing entirely the photoresist pattern, a gate metal evaporation process for evaporating a metal which is in ohmic contact with the P type InP layer, to thereby form a gate electrode, a selective etching process of the P type InP layer and the GaInAs(P) layer for etching selectively the P type InP layer by using an etching mask as a gate metal and for forming large under-cuts near both sides of the PN junction by selectively etching the GaInAs(P) layer which is exposed on surface after said selective etching is completed, a source and drain metal evaporation process for forming source and drain electrodes by evaporating a metal which is in ohmic contact with the N type InP layer, to thereby obtain a gate length L shorter than a length W on mask determined by the lithography method and to obtain electrodes by a self-aligning method.

Claim 2

A method for manufacturing a heterojunction type field effect transistor comprising: a first epitaxy growth process for growing a N type GaInAs(P) channel layer, a N type InP layer and a GaInAs(P) layer on a semi-insulating substrate, a selective etching process of the GaInAs(P) layer and the N type InP layer for selectively anisotropically etching only the GaInAs(P) layer by using a selective etching solution, and selectively etching the N type InP layer additionally, after lithographically forming an etching mask of photoresist, a second epitaxy growth process for growing a P type InP layer for a PN junction after removing entirely the photoresist pattern, a gate metal evaporation process for evaporating a metal which is in ohmic contact with the P type InP layer, to thereby form a gate electrode, a selective etching process of the P type InP layer and the GaInAs(P) layer for etching selectively the P type InP layer by using an etching mask as a gate metal and for forming large under-cuts near both sides of the PN junction by selectively etching the GaInAs(P) layer which is exposed on surface after said selective etching is completed, a source and drain metal evaporation process for forming source and drain electrodes by evaporating a metal which is in ohmic contact with the N type InP layer, to thereby obtain a gate length L shorter than a length W on mask determined by the lithography method and to obtain electrodes by a self-aligning method.

Claim 6

A method for manufacturing a junction type field effect transistor comprising: a first epitaxy growth process for growing a GaInAs channel layer as a channel layer in a semi-insulating substrate and, thereafter, growing a InP layer as a second layer thereon a selective etching process of the InP layer for selectively anisotropically etching only the InP layer by using a selective etching solution, after lithographically forming an etching mask of photoresist, a second epitaxy growth process for growing a P type InP layer for a PN junction after removing entirely the photoresist pattern, a gate metal evaporation process for evaporating a metal which is in ohmic contact with the P type GaInAs layer, to thereby form a gate electrode, a selective etching process of the P type GaInAs layer and the InP layer for etching selectively the GaInAs layer by using an etching mask as a gate metal and for forming large under-cuts near both sides of the PN junction by selectively etching the InP layer which is exposed on the surface after the selective etching is completed, a source and a drain metal evaporation process for forming source and drain electrodes by evaporating a metal which is in ohmic contact with the GaInAs channel layer formed on the substrate to thereby obtain a gate length L shorter than a width W on mask determined by the lithography and to obtain an electrode by a self-aligning method.

Claim 7

A method for manufacturing a junction type field effect transistor comprising: a first epitaxy growth process for growing a GaInAs channel layer as a channel layer in a semi-insulating substrate and, thereafter, growing a InP layer as a second layer thereon a selective etching process of the InP layer for selectively anisotropically etching only the InP layer by using a selective etching solution, after lithographically forming an etching mask of photoresist, a second epitaxy growth process for growing a P type InP layer for a PN junction after removing entirely the photoresist pattern, a gate metal evaporation process for evaporating a metal which is in ohmic contact with the P type GaInAs layer, to thereby form a gate electrode, a selective etching process of the P type GaInAs layer and the InP layer for etching selectively the GaInAs layer by using an etching mask as a gate metal and for forming large under-cuts near both sides of the PN junction by selectively etching the InP layer which is exposed on the surface after the selective etching is completed, a source and a drain metal evaporation process for forming source and drain electrodes by evaporating a metal which is in ohmic contact with the GaInAs channel layer formed on the substrate to thereby obtain a gate length L shorter than a width W on mask determined by the lithography and to obtain an electrode by a self-aligning method.