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US4075652A
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US
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Junction gate type gaas field-effect transistor and method of forming
Assignee: Panasonic Holdings Corp
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Filing: 1977-05-05
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Granted: 1978-02-21
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Expires: 1997-05-05
Abstract
Abstract The invention discloses a heterojunction Type GaAs field-effect transistor of the type in which a channel region consists of an n-type GaAs layer with a higher mobility and a gate region consists of a p-type Ga 1-y Al y As layer which is grown heteroepitaxially. The length of the gate is of the order of microns, and a gate, source and drain electrodes are self-aligned. The gate region is etched in the form of a mushroom with the use of an etchant which etched the GaAlAs layer and the Ga-As layer at different etching rates so that the gate, source and drain electrodes may be formed by only one vacuum deposition of a metal such as aluminum.
Inventors
- 👤 Shotaro Umebachi
- 👤 Gota Kano
- 👤 Morio Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:52
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/646; H10D; H10D30/00; H10D30/80; H10D30/801; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/072; Y10S148/139; Y10S148/143
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
126 words
A junction gate type field-effect transistor comprising a semiconductor substrate of p-type GaAs, a semiconductor layer of n-type Ga 1-x Al x As (0 ≦ x ≦ 0.1), a semiconductor gate region of p-type Ga 1-y Al y As (0.2 ≦ y ≦ 0.8) forming a heterojunction with said n-type layer, an electrode region of p-type Ga 1-z Al z As (0 ≦ z ≦ 0.1) contiguous with said gate region, the width of said gate region being less than the width of said electrode region; and first and second ohmic electrodes disposed of said n-type layer and spaced apart from each other by said gate and electrode regions, whereby the conductivity of said semiconductor layer may be controlled by the electric field across said heterojunction.
Claim 2
Dependent Claim
126 words
A junction gate type field-effect transistor comprising a semiconductor substrate of p-type GaAs, a semiconductor layer of n-type Ga 1-x Al x As (0 ≦ x ≦ 0.1), a semiconductor gate region of p-type Ga 1-y Al y As (0.2 ≦ y ≦ 0.8) forming a heterojunction with said n-type layer, an electrode region of p-type Ga 1-z Al z As (0 ≦ z ≦ 0.1) contiguous with said gate region, the width of said gate region being less than the width of said electrode region; and first and second ohmic electrodes disposed of said n-type layer and spaced apart from each other by said gate and electrode regions, whereby the conductivity of said semiconductor layer may be controlled by the electric field across said heterojunction.
Claim 3
Dependent Claim
26 words
A junction gate type field-effect transistor as set forth in claim 1 wherein said gate and electrode regions are etched in the form of a mushroom.
References Cited (Backward Citations)
US3833435A
Cited
US3906541A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-20 | 1981-08-22 | 1982-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-20 | 1985-08-22 | 1986-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-20 | 1989-08-22 | 1990-02-21 | $7700.00 | Window Closed / Lapsed |