US5115456A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mask for exposing wafer with radiation and its exposing method
Assignee: Hitachi Ltd
•
Filing: 1989-12-08
•
Granted: 1992-05-19
•
Expires: 2009-12-08
Abstract
Abstract A mask for exposing a wafer with radiation and its exposition method in which the radiation exposure mask is provided with at least two radiation exposure windows which each include a mask pattern of a smaller pattern area obtained by dividing a pattern area constituting an integrating circuit chip into a plurality of the areas, and a semiconductor wafer is exposed with radiation while the radiation exposure mask is intermittently moved by a distance of the size of the small pattern area.
Inventors
- 👤 Takeshi Kimura
- 👤 Shinji Kuniyoshi
- 👤 Akihiko Kishimoto
- 👤 Takashi Soga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:04
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/22; G03F7/00; G03F7/70; G03F7/70425; G03F7/70475
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
115 words
A mask for exposing a wafer with radiation comprising: a thin film through which the radiation can pass; a mask pattern disposed at a first side of said thin film for absorbing the radiation, said mask pattern having a plurality of rectangular mask pattern areas arranged at prescribed intervals, and each of said rectangular mask pattern areas corresponding to a respective predetermined divided area of a single integrated circuit chip of the wafer; and a support frame positioned at a second side of said thin film for supporting said thin film, said support frame having a plurality of radiation exposure windows respectively aligned with said plurality of rectangular mask pattern areas of said mask pattern.
Claim 2
Dependent Claim
115 words
A mask for exposing a wafer with radiation comprising: a thin film through which the radiation can pass; a mask pattern disposed at a first side of said thin film for absorbing the radiation, said mask pattern having a plurality of rectangular mask pattern areas arranged at prescribed intervals, and each of said rectangular mask pattern areas corresponding to a respective predetermined divided area of a single integrated circuit chip of the wafer; and a support frame positioned at a second side of said thin film for supporting said thin film, said support frame having a plurality of radiation exposure windows respectively aligned with said plurality of rectangular mask pattern areas of said mask pattern.
Claim 3
Dependent Claim
46 words
A mask for exposing a wafer with radiation according to claim 1, wherein the radiation exposure windows of said support frame are spaced apart from one another by a distance corresponding to an integral multiple of a width of one of said rectangular mask pattern areas.
Claim 4
Dependent Claim
20 words
A mask for exposing a wafer with radiation according to claim 1 or 2, wherein said radiation is X-ray radiation.
Claim 5
Dependent Claim
86 words
A mask for exposing a wafer with radiation according to claim 1 or 2, wherein a first one of said rectangular mask pattern areas and a second one of said rectangular mask pattern areas each comprise at least one line pattern, and each line of the line patterns which crosses a boundary between said first rectangular mask pattern area and said second rectangular mask pattern area is enlarged at the boundary, at least in width, with respect to all other non-boundary portions of the crossing line.
Claim 6
Dependent Claim
102 words
A radiation exposure method comprising the steps of: disposing a radiation exposing mask over a wafer covered with a resist, said radiation exposing mask, including a mask pattern capable of absorbing radiation, said mask pattern having a plurality of rectangular mask pattern areas arranged at prescribed intervals, and each of said rectangular mask pattern areas corresponding to a respective predetermined divided area of a single integrated circuit chip of the wafer; and alternately irradiating said resist by passing the radiation through said mask and moving one of said mask and said wafer relative to the other of said mask and said wafer.
Claim 7
Dependent Claim
102 words
A radiation exposure method comprising the steps of: disposing a radiation exposing mask over a wafer covered with a resist, said radiation exposing mask, including a mask pattern capable of absorbing radiation, said mask pattern having a plurality of rectangular mask pattern areas arranged at prescribed intervals, and each of said rectangular mask pattern areas corresponding to a respective predetermined divided area of a single integrated circuit chip of the wafer; and alternately irradiating said resist by passing the radiation through said mask and moving one of said mask and said wafer relative to the other of said mask and said wafer.
Claim 8
Dependent Claim
22 words
A radiation exposure method according to claim 5, wherein patterns are replicated on said wafer by reducing and projecting said mask pattern.
Claim 9
Dependent Claim
14 words
A radiation exposure method according to claim 5, wherein said radiation is X-ray radiation.
Claim 10
Dependent Claim
136 words
A radiation exposure method utilizing a radiation exposing mask disposed over a wafer, said radiation exposing mask including a mask pattern capable of absorbing radiation, said mask pattern having a plurality of mask pattern areas arranged at prescribed intervals, each of said rectangular mask pattern areas corresponding to a respective divided area of a single integrated circuit chip of the wafer, and said method comprising the steps of: irradiating a portion of said integrated circuit chip corresponding to one of said rectangular mask pattern areas; adjusting a positional relationship between said mask and said integrated circuit chip of the wafer; and repeating the irradiating and adjusting steps until a complete circuit is formed on said integrated circuit chip of the wafer over each of the predetermined divided areas of said integrated circuit chip of the wafer.
Claim 11
Dependent Claim
136 words
A radiation exposure method utilizing a radiation exposing mask disposed over a wafer, said radiation exposing mask including a mask pattern capable of absorbing radiation, said mask pattern having a plurality of mask pattern areas arranged at prescribed intervals, each of said rectangular mask pattern areas corresponding to a respective divided area of a single integrated circuit chip of the wafer, and said method comprising the steps of: irradiating a portion of said integrated circuit chip corresponding to one of said rectangular mask pattern areas; adjusting a positional relationship between said mask and said integrated circuit chip of the wafer; and repeating the irradiating and adjusting steps until a complete circuit is formed on said integrated circuit chip of the wafer over each of the predetermined divided areas of said integrated circuit chip of the wafer.
References Cited (Backward Citations)
US3742230A
Cited
US3873824A
Cited
US3974382A
Cited
US4260670A
Cited
US4301237A
Cited
EP0069265A1
Cited
JPS6318353A
Cited
JPS6318352A
Cited
JPS6318351A
Cited
EP0266275A2
Cited
US4881257A
Cited
EP0364929A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |