Patent US5113418A successfully refreshed from Google Patents.
US5113418A
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Elastic buffer for local area network
Assignee: Texas Instruments Inc
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Filing: 1989-10-06
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Granted: 1992-05-12
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Expires: 2009-10-06
Abstract
Abstract An elastic buffer for absorbing frequency jitter or drift of an incoming data signal which includes a serial stack of data registers. These data registers are used for storing data bits from an incoming data stream one at a time with each bit adjacent a next earlier bit at a frequency equal to the frequency of the incoming data and also for releasing stored bits onto an output data line. The stored bits are released one at a time at a predetermined fixed rate equal to the average frequency of incoming data from a number of registers away from the register into which data is being written which depends on the frequency difference between incoming data and the fixed rate aforesaid.
Inventors
- 👤 Andre Szczepanek
- 👤 George Buchanan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:13
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
113 words
A circuit for absorbing frequency jitter of data bits incoming on an input data line, comprising: a serial connected loop stack of data register cells; circuitry for storing each incoming data bit in a selected one of said cells within said serial connected loop stack wherein each bit is stored at a first frequency in a cell adjacent a cell in which is stored a next earlier bit; and circuitry for directing stored data from a selected one of said cells within said serial connected loop stacked onto an output data line at a second frequency, wherein said circuitry for directing is operable to direct data bits simultaneously with said circuitry for storing.
Claim 2
Dependent Claim
113 words
A circuit for absorbing frequency jitter of data bits incoming on an input data line, comprising: a serial connected loop stack of data register cells; circuitry for storing each incoming data bit in a selected one of said cells within said serial connected loop stack wherein each bit is stored at a first frequency in a cell adjacent a cell in which is stored a next earlier bit; and circuitry for directing stored data from a selected one of said cells within said serial connected loop stacked onto an output data line at a second frequency, wherein said circuitry for directing is operable to direct data bits simultaneously with said circuitry for storing.
Claim 3
Dependent Claim
29 words
The circuit for absorbing frequency jitter of claim 1 wherein said data bits arrive at a third frequency and wherein said first frequency is equal to said third frequency.
Claim 4
Dependent Claim
29 words
The circuit for absorbing frequency jitter of claim 1 wherein said data bits arrive at a third frequency and said second frequency equals the average of said third frequency.
Claim 5
Dependent Claim
31 words
The circuit for absorbing frequency jitter of claim 1 wherein said circuitry for storing said data bits is operable to store said data bits one at a time into said cells.
Claim 6
Dependent Claim
74 words
The circuit for absorbing frequency jitter of claim 1 wherein said circuitry for directing comprises: a pluratily of output gates each coupled between the output data line and an output of a corresponding one of said cells; and an output pointer circuit selectively coupled to each of said output gates and operable to open each output gate when coupled thereto to allow transmission of a data bit from said cell to the output line.
Claim 7
Dependent Claim
84 words
The circuit for absorbing frequency jitter of claim 5 wherein said output pointer comprises a plurality of latches, each one of said latches corresponding to one output gate and one cell of said stack, wherein all latches except a selected latch will operate in a first state while the selected latch operates in a second state, the second state operating to open the output gate corresponding to the selected latch and wherein the next latch to be selected is adjacent the currently selected latch.
Claim 8
Dependent Claim
75 words
The circuit for absorbing frequency jitter of claim 1 wherein said circuitry for storing comprises: a plurality of input gates each coupled between the input data line and an input of a corresponding one of said cells; and an input pointer circuit selectively coupled to each of said input gates and operable to open each input gate when coupled thereto to allow transmission of a data bit from said input line into a corresponding cell.
Claim 9
Dependent Claim
84 words
The circuit for absorbing frequency jitter of claim 7 wherein said input pointer comprises a plurality of latches, each one of said latches corresponding to one input gate and one cell of said stack, wherein all latches except a selected latch will operate in a first state while the selected latch operates in a second state, the second state operating to open the input gate corresponding to the selected latch, and wherein the next latch to be selected is adjacent the currently selected latch.
Claim 10
Dependent Claim
47 words
The circuit for absorbing frequency jitter of claim 1 and further comprising circuitry for generating an error detection signal when the cell into which a data bit is being stored is contiguous to a cell from which a data bit is being directed to the output line.
Claim 11
Dependent Claim
31 words
The circuit for absorbing frequency jitter of claim 9 and further comprising circuitry for resetting said storing circuitry and said directing circuitry when said generating circuitry generates an error detection signal.
Claim 12
Dependent Claim
126 words
A circuit for absorbing frequency jitter of data bits incoming on an input data line, comprising: a serial connected loop stack of data register cells; circuitry for storing each incoming data bit in a selected one of said cells within said serial connected loop stack wherein each bit is stored at a first frequency; and circuitry for directing data from a selected one of said cells within said serial connected loop stack onto a output data line at a second frequency, wherein said circuitry for directing is operable to direct data bits simultaneously with said circuitry for storing and wherein said circuitry for directing directs data to said output line from the specific cell which the data was originally stored in by said circuitry for storing.
Claim 13
Dependent Claim
126 words
A circuit for absorbing frequency jitter of data bits incoming on an input data line, comprising: a serial connected loop stack of data register cells; circuitry for storing each incoming data bit in a selected one of said cells within said serial connected loop stack wherein each bit is stored at a first frequency; and circuitry for directing data from a selected one of said cells within said serial connected loop stack onto a output data line at a second frequency, wherein said circuitry for directing is operable to direct data bits simultaneously with said circuitry for storing and wherein said circuitry for directing directs data to said output line from the specific cell which the data was originally stored in by said circuitry for storing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |