Method of manufacturing a compound semiconductor device

Claim 1

A manufacturing process of a compound semiconductor device, comprising: the first step of forming successively a first compound semiconductor layer, a second compound semiconductor layer for a source and a drain region, and a first structural layer on a semiconductor substrate; the second step of forming a first resist pattern having a first opening on the first structural layer; the third step of etching an area of the first structural layer that is exposed through the first opening with the first resist pattern being used as a mask to thereby expose the second semiconductor layer, and thereafter removing the first resist pattern; the fourth step of forming successively a second structural layer and a third structural layer on the exposed area of the second semiconductor layer and the entire first structural layer, the second structural layer being dissoluble by a particular etchant and the third structural layer being less dissoluble by the particular etchant than the second structural layer; the fifth step of forming on the third structural layer a second resist pattern having a second opening that is located over the etched area of the first structural layer and closer to the source region than to the drain region; the sixth step of etching the second and third structural layers with the second resist pattern being used as a mask to thereby expose the second semiconductor layer through a third opening of the third structural layer, and thereafter removing the second resist pattern; the seventh step of side-etching the second structural layer with the particular etchant through the third opening of the third structural layer to produce a fourth opening in the second structural layer; the eighth step of etching the exposed area of the second semiconductor layer through the fourth opening of the second structural layer to thereby expose the first semiconductor layer and to form the source and drain regions in the second semiconductor layer; and the ninth step of vapor-depositing a gate metal vertically on the exposed area of the first semiconductor layer.