Digital frequency multiplication and data serialization circuits

Claim 2

A clock frequency multiplication and data serialization circuit for converting Q parallel data bits having an associated clock signal of first frequency and period into a serial data stream having a frequency which is a multiple of said first frequency, said circuit comprising: clock phase generating means coupled to receive the clock signal associated with said Q parallel data bits, said generating means outputting in response thereto Q synchronous clocks each of different phase per clock signal period; and logic circuitry coupled to receive said Q synchronous clocks and the Q parallel data bits, said logic circuitry using each of said Q synchronous clocks to gate a respective one of said Q parallel data bits such that the Q parallel data bits are sequentially output therefrom as a serial data stream having a frequency which is a multiple of said first frequency.

Claim 3

The frequency multiplication and data serialization circuit of claim 1, wherein said logic circuitry includes: means for detecting each of said Q synchronous clocks and outputting a signal pulse in response thereto; a plurality of AND gates, each AND gate being coupled to receive at a first input one of said signal pulses and at a second input a respective one of the parallel data bits; and OR circuit means coupled to receive in parallel the output signals of said plurality of AND Gates and combine said AND gate output signals into the serial data stream.

Claim 4

The frequency multiplication and data serialization circuit of claim 2, wherein said clock detecting means includes a plurality of edge detectors, each edge detector being coupled to receive one of said Q synchronous clocks output from said clock phase generating means, each edge detector outputting a signal pulse in response to a received clock.

Claim 5

The frequency multiplication and data serialization circuit of claim 3, wherein said clock detecting means includes Q edge detectors, said edge detectors each outputting a signal pulse on the rising edge of a received clock, each detector including a delay and an A NOT B logic circuit having an A input and a B input, the A input to said A NOT B logic and an input to said delay each being coupled to receive one of the Q synchronous clocks, the output of said delay being coupled to the B input to said A NOT B logic, an output pulse from said A NOT B logic circuit comprising said edge detector signal pulse.

Claim 6

The frequency multiplication and data serialization circuit of claim 3, wherein said clock detecting means includes Q edge detectors, said edge detectors each outputting a signal pulse on the falling edge of a received clock, each detector including a delay and an A NOT B logic circuit having an A input and a B input, the B input to said A NOT B logic and an input to said delay being coupled to receive one of the Q synchronous clocks, the output of said delay being coupled to the A input of said A NOT B logic, an output pulse from said A NOT B logic comprising said edge detector signal pulse.

Claim 7

The frequency multiplication and data serialization circuit of claim 3, wherein said clock detecting means includes Q edge detectors, said edge detectors each outputting a signal pulse on the rising edge of a received clock, each detector including a delay, an invertor and an AND gate, one input to said AND gate and an input to said delay each being coupled to receive one of the Q synchronous clocks, the output of said delay being coupled to the input of said invertor, the invertor output being coupled to a second input to said AND gate, an output from said AND gate comprising said edge detector signal pulse.

Claim 8

The frequency multiplication and data serialization circuit of claim 3, wherein said clock detecting means includes Q edge detectors, said edge detectors each outputting a signal pulse on the falling edge of a received clock, each detector including a delay, an invertor and an AND gate, the input to said invertor and the input to said delay each being coupled to receive one of the Q synchronous clocks, the output of said invertor being coupled to a first input to said AND gate and the output of said delay being coupled to a second input to said AND gate, an output from said AND gate comprising said edge detector signal pulse.

Claim 9

The frequency multiplication and data serialization circuit of claim 2, wherein said clock phase generating means comprises a delay line having Q taps, each of said taps outputting one of said Q synchronous clocks of different phase.

Claim 10

The frequency multiplication and data serialization circuit of claim 8, wherein said detecting means comprises Q separate detecting means, an input to each of said Q detecting means being coupled to one of said delay line taps, and wherein said plurality of AND gates comprise Q AND gates, one input of each of said Q AND gates being coupled to an output of a respective one of said Q detecting means.

Claim 11

A clock frequency multiplication and data serialization circuit for converting Q parallel data bits having an associated clock signal of first frequency and period into a serial data stream having a frequency which is Q times the first frequency, said circuit comprising: a delay line coupled to receive the clock signal associated with said Q parallel data bits, said delay line having Q taps, said taps each outputting one of Q synchronous delay clocks each of different phase; Q clock detecting means, each clock detecting means being coupled to a respective delay line tap to receive the corresponding delay clock, said clock detecting means each outputting a signal pulse in response to a received delay clock; Q AND gates, each AND gate being coupled at a first input to an output of a clock detecting means for receiving the corresponding signal pulse and at a second input to a respective one of said Q parallel data bits; and OR circuit means having Q inputs, outputs of said AND gates being coupled in parallel to the Q inputs of said OR circuit means, said OR circuit means combining output signals from said AND Gates into a serial data stream having a frequency which is Q times said first frequency.

Claim 12

A clock frequency multiplication and data serialization circuit for converting Q parallel data bits having an associated clock signal of first frequency and period into a serial data stream having a frequency which is Q times the first frequency, said circuit comprising: a delay line coupled to receive the clock signal associated with said Q parallel data bits, said delay line having Q taps, said taps each outputting one of Q synchronous delay clocks each of different phase; Q clock detecting means, each clock detecting means being coupled to a respective delay line tap to receive the corresponding delay clock, said clock detecting means each outputting a signal pulse in response to a received delay clock; Q AND gates, each AND gate being coupled at a first input to an output of a clock detecting means for receiving the corresponding signal pulse and at a second input to a respective one of said Q parallel data bits; and OR circuit means having Q inputs, outputs of said AND gates being coupled in parallel to the Q inputs of said OR circuit means, said OR circuit means combining output signals from said AND Gates into a serial data stream having a frequency which is Q times said first frequency.

Claim 13

The clock frequency multiplication and data serialization circuit of claim 10, wherein said circuit produces return-to-zero data serialization and wherein said Q clock detecting means comprise Q edge detectors, said edge detectors each including a delay therein, each edge detector delay being less than a delay between adjacent delay clocks of the delay line.

Claim 14

The clock frequency multiplication and data serialization circuit of claim 10, wherein said circuit produces nonreturn-to-zero data serialization, and wherein said Q clock detecting means each comprises an A NOT B logic circuit having an A input and a B input, the A input of said A NOT B logic being coupled to receive a f(m-1)delayed clock of the delay line and the B input to said A NOT B logic being coupled to receive a f(m) delayed clock of the delay line, wherein M=1, 2, 2, . . . , Q-1.

Claim 15

The clock frequency multiplication and data serialization circuit of claim 10, wherein said circuit produces a combination return to zero and nonreturn to zero data serialization, and wherein at least one of said Q clock detecting means comprises an edge detector, said edge detector including a delay therein less than a delay between adjacent delay clocks of the delay line, and wherein said Q clock detecting means includes at least an A NOT B logic circuit having an A input and a B input, the A input of said A NOT B logic being coupled to receive a first delayed clock of the delay line and the B input to said A NOT B logic being coupled to receive a second delayed clock of the delay line, said second delayed clock comprising the next subsequent delayed clock from said first delay clock.

Claim 16

A frequency multiplication and synchronization circuit for generating a synchronous high frequency signal from a low frequency signal, said circuit comprising: clock phase generating means coupled to receive the low frequency signal and output in response thereto Q synchronous clocks each of different phase; Q clock detectors coupled to receive one of said Q synchronous clocks and output a signal pulse in response thereto; and logic circuit means coupled to receive in parallel the output signal pulses of said Q clock detectors, and output therefrom said synchronous high frequency signal.

Claim 17

A frequency multiplication and synchronization circuit for generating a synchronous high frequency signal from a low frequency signal, said circuit comprising: clock phase generating means coupled to receive the low frequency signal and output in response thereto Q synchronous clocks each of different phase; Q clock detectors coupled to receive one of said Q synchronous clocks and output a signal pulse in response thereto; and logic circuit means coupled to receive in parallel the output signal pulses of said Q clock detectors, and output therefrom said synchronous high frequency signal.

Claim 18

The frequency multiplication and synchronization circuit of claim 14, wherein said clock phase generating means comprises a delay line having Q taps, each tap outputting one of said Q synchronous clocks of different phase.

Claim 19

The frequency multiplication and synchronization circuit of claim 15, wherein said Q clock detecting means comprise Q edge detectors, each edge detector outputting a signal pulse on one of the rising and falling edges of the received clock.

Claim 20

The frequency multiplication and synchronization circuit of claim 16, wherein said logic circuit means comprises an OR logic circuit.

Claim 21

The frequency multiplication and synchronization circuit of claim 16 wherein said logic circuit means comprises a multiplexer.

Claim 22

The frequency multiplication and synchronization circuit of claim 14, wherein said logic circuit means further functions to simultaneously convert Q parallel data bits into a serial data stream comprising said synchronous high frequency signal.

Claim 23

The frequency multiplication and synchronization circuit of claim 19, wherein said logic circuit means comprises: Q AND gates, each AND gate being coupled at a first input to an output of a clock detector for receiving the corresponding signal pulse and at a second input to a respective one of said Q parallel data bits; and OR circuit means having Q inputs, outputs of said AND gates being coupled in parallel to the Q inputs of said OR circuit means, said OR circuit means combining output signals from said AND gates to form said serial data stream.

Claim 24

A clock frequency multiplication and data serialization circuit for converting Q parallel data bits having an associated clock signal of first frequency and period into a serial data stream having a frequency which is a multiple of said first frequency, said circuit comprising: clock phase generating means coupled to receive the clock signal associated with said Q parallel data bits, said generating means outputting in response thereto Q synchronous clocks each of different phase per clock signal period; and logic circuitry means coupled to receive said Q synchronous clocks and the Q parallel data bits, said logic circuitry means functioning to simultaneously frequency multiply and data serialize the Q parallel data bits to provide a serial data stream having a frequency which is a multiple of said first frequency.

Claim 25

A clock frequency multiplication and data serialization circuit for converting Q parallel data bits having an associated clock signal of first frequency and period into a serial data stream having a frequency which is a multiple of said first frequency, said circuit comprising: clock phase generating means coupled to receive the clock signal associated with said Q parallel data bits, said generating means outputting in response thereto Q synchronous clocks each of different phase per clock signal period; and logic circuitry means coupled to receive said Q synchronous clocks and the Q parallel data bits, said logic circuitry means functioning to simultaneously frequency multiply and data serialize the Q parallel data bits to provide a serial data stream having a frequency which is a multiple of said first frequency.