Clock jitter suppressing circuit

Claim 1

A clock jitter suppressing circuit comprising control means for generating a selection signal based on jitter information of a clock signal, delay means for sequentially delaying the clock signal and outputting respective delay outputs, and selection means for selecting one of the delay outputs on the basis of the selection signal. wherein said delay means sequentially delays the clock signal at time intervals sufficiently shorter than a period of the clock signal and outputs respective delay outputs, said selection means selects and outputs one of the delay outputs from said delay means which is determined in accordance with the selection signal. said control means generates a selection signal for selecting a predetermined one of the delay outputs when no jitter is caused in the clock signal, and every time jitter is caused in the clock signal, generates a selection signal for selecting a delay output which is shifted by an amount corresponding to a phase amount of the jitter in a direction to cancel a polarity of the jitter, wherein said control means comprises jitter detecting means for generating an up/down count signal in a direction to cancel a phase jitter component in accordance with a polarity and a phase amount of the phase jitter component, and an up/down counter for performing a count operating in accordance with the up/down count signal, and is designed to output an up/down counter output as a selection signal.