Semiconductor integrated circuit chip having an identification circuit therein

Claim 2

In a semiconductor integrated circuit chip having a pair of power supply terminals, a plurality of input terminals and an identification circuit means connected between one of said power supply terminals and one of said input terminals, the improvement wherein said identification circuit means comprises: a voltage limiter for limiting the input potential difference between said one power supply terminal and said one input terminal to a predetermined limiting voltage level; and option means connected in series to said voltage limiter for providing identification information indicative of said chip.

Claim 3

A semiconductor integrated chip as defined in claim 1, wherein said voltage limiter comprises a plurality of serially connected MOS transistors, each of said MOS transistors having a gate connected to a drain thereof, whereby said predetermined limiting voltage level is set to be a sum of the threshold voltages of said MOS transistors.

Claim 4

A semiconductor integrated circuit chip as defined in claim 1, wherein said option means comprises a fuse which is optionally one of connected or disconnected.

Claim 5

A semiconductor integrated circuit chip as defined in claim 1, wherein said option means comprises a MOS transistor having a gate and a source which are optionally one of connected or disconnected by a metal wire.

Claim 6

A semiconductor integrated circuit as defined in claim 1, wherein said option means comprises a plurality of identification paths connected in parallel, each said identification path having a MOS transistor connected in series to a fuse, said MOS transistor having a gate connected to a drain thereof, and said identification information being set according to said fuses being optionally one of connected or disconnected.

Claim 7

In a semiconductor integrated circuit chip having a pair of power supply terminals, at least three input terminals and an identification circuit means connected with one of said power supply terminals and with said three input terminals, the improvement wherein said identification circuit means comprises: voltage limiting means for limiting the potential difference between said one power supply terminal and one of said three input terminals to a predetermined limiting voltage level and for generating a predetermined control voltage by dividing the limiting voltage level; option means connected between the remaining two of said three input terminals for providing identification information indicative of said chip; and switch means connected in series to said option means, said switch means being controlled by said control voltage supplied from said voltage limiting means.

Claim 8

In a semiconductor integrated circuit chip having a pair of power supply terminals, at least three input terminals and an identification circuit means connected with one of said power supply terminals and with said three input terminals, the improvement wherein said identification circuit means comprises: voltage limiting means for limiting the potential difference between said one power supply terminal and one of said three input terminals to a predetermined limiting voltage level and for generating a predetermined control voltage by dividing the limiting voltage level; option means connected between the remaining two of said three input terminals for providing identification information indicative of said chip; and switch means connected in series to said option means, said switch means being controlled by said control voltage supplied from said voltage limiting means.

Claim 9

A semiconductor integrated circuits chip as defined in claim 6, wherein said voltage limiting means comprises: a plurality of serially connected MOS transistors, each of which has a gate connected to a respective drain thereof; and a resistor connected to said plurality of MOS transistors, whereby said limiting voltage level is a sum of a terminal voltage of said resistor and the threshold voltages of said MOS transistors, and said control voltage is said terminal voltage of said resistor.

Claim 10

A semiconductor integrated circuits chip as defined in claim 6, wherein said option means comprises a plurality of fuses and said switch means comprises a plurality of MOS transistors, each of said plurality of fuses being serially connected to a corresponding one of said plurality of said MOS transistors, said MOS transistors having gates coupled to receive said control voltage, and said identification information of said chip being determined according to whether said fuses are one of connected or disconnected.

Claim 11

An integrated circuit chip comprising: internal circuit means; a pair of power supply terminals for supplying power to said internal circuit means; a plurality of input terminals for supplying signals to said internal circuit means; and identification circuit means, coupled between one of said power supply terminals and one of said input terminals, comprising: voltage limiting means for limiting a potential difference between said one power supply terminal and said one input terminal to a predetermined voltage level; and option means coupled to said voltage limiting means for optionally permitting current to flow therethrough; whereby said chip is identified according to whether said current flows through said identification circuit means.

Claim 12

An integrated circuit chip comprising: internal circuit means; a pair of power supply terminals for supplying power to said internal circuit means; a plurality of input terminals for supplying signals to said internal circuit means; and identification circuit means, coupled between one of said power supply terminals and one of said input terminals, comprising: voltage limiting means for limiting a potential difference between said one power supply terminal and said one input terminal to a predetermined voltage level; and option means coupled to said voltage limiting means for optionally permitting current to flow therethrough; whereby said chip is identified according to whether said current flows through said identification circuit means.

Claim 13

An integrated circuit chip comprising: internal circuit means; a pair of power supply terminals for supplying power to said internal circuit means; at least three input terminals for supplying signals to said internal circuit means; and identification circuit means, coupled to one of said power supply terminals and at least three of said input terminals, comprising: voltage limiting means, coupled between said one power supply terminal and a first of said three input terminals, for limiting a potential difference between said one power supply terminal and said first input terminal to a predetermined voltage level and for generating a control voltage, said voltage limiting means comprising a plurality of MOS transistors connected in series with a resistor; a plurality of identification current paths coupled in parallel between a second and a third of said input terminals, each said path comprising a MOS transistor connected in series with a disconnectable member, said MOS transistor having a gate coupled to receive said control voltage generated by said voltage limiting means; whereby said chip is identifiable according to a sum of currents flowing through said plurality of identification current paths.

Claim 14

An integrated circuit chip comprising: internal circuit means; a pair of power supply terminals for supplying power to said internal circuit means; at least three input terminals for supplying signals to said internal circuit means; and identification circuit means, coupled to one of said power supply terminals and at least three of said input terminals, comprising: voltage limiting means, coupled between said one power supply terminal and a first of said three input terminals, for limiting a potential difference between said one power supply terminal and said first input terminal to a predetermined voltage level and for generating a control voltage, said voltage limiting means comprising a plurality of MOS transistors connected in series with a resistor; a plurality of identification current paths coupled in parallel between a second and a third of said input terminals, each said path comprising a MOS transistor connected in series with a disconnectable member, said MOS transistor having a gate coupled to receive said control voltage generated by said voltage limiting means; whereby said chip is identifiable according to a sum of currents flowing through said plurality of identification current paths.

Claim 15

An integrated circuit chip according to claim 10, wherein said disconnectable member comprises a fuse which may be optionally connected or disconnected.

Claim 16

An integrated circuit chip according to claim 10, wherein said disconnectable member comprises a metal wire disposed between a gate and a source of a MOS transistor, said gate and source being optionally connected or disconnected by said metal wire.