Method for forming self-aligned conducting pillars in an (IC) fabrication process

Claim 1

A method of forming parallel spaced conducting pillars in a semiconductor integrated circuit comprising: depositing a conducting layer (conductor 1) on a silicon substrate having an insulating layer formed thereon; depositing an insulator on the conducting layer; photo-etching the conducting layer to form separate parallel spaced conductor lines with spaces having a width of C1 therebetween; conformally depositing and anisotropically etching an insulating film on the sidewalls of the parallel spaced conductor lines to form insulating spacers on the conductor lines while leaving gaps between the insulating spacers; depositing a conducting film (conductor 2) over the parallel spaced conductor lines and into the gaps to a thickness of tc2 which completely fills the gaps; blanket etching the conducting film stopping the etch after etching approximately a thickness of tc2 to form planarized conducting pillars within the gaps; photo-etching to form contact vias to the conducting pillars over-sizing a photo mask in a direction parallel to the parallel spaced conducting lines to self-align the conducting pillars to the conducting lines; and forming a multilevel interconnect to the conducting pillars.

Claim 2

A method of forming parallel spaced conducting pillars in a semiconductor integrated circuit comprising: depositing a conducting layer (conductor 1) on a silicon substrate having an insulating layer formed thereon; depositing an insulator on the conducting layer; photo-etching the conducting layer to form separate parallel spaced conductor lines with spaces having a width of C1 therebetween; conformally depositing and anisotropically etching an insulating film on the sidewalls of the parallel spaced conductor lines to form insulating spacers on the conductor lines while leaving gaps between the insulating spacers; depositing a conducting film (conductor 2) over the parallel spaced conductor lines and into the gaps to a thickness of tc2 which completely fills the gaps; blanket etching the conducting film stopping the etch after etching approximately a thickness of tc2 to form planarized conducting pillars within the gaps; photo-etching to form contact vias to the conducting pillars over-sizing a photo mask in a direction parallel to the parallel spaced conducting lines to self-align the conducting pillars to the conducting lines; and forming a multilevel interconnect to the conducting pillars.

Claim 7

A method of forming parallel spaced self-aligned conducting pillars in a semiconductor integrated circuit for forming a multilevel interconnect comprising: depositing a conducting layer on a silicon substrate having a gate oxide layer formed thereon; depositing an insulator oxide on the conducting layer; photo-etching to form parallel spaced conducting lines in the conducting layer having spaces of a width C1 therebetween; conformally depositing and anisotropically etching an insulator oxide to form insulating spacers on the sidewalls of the parallel spaced conducting lines while leaving gaps therebetween; conformally depositing a conducting film to a thickness of tc2 over the parallel spaced conducting lines and into the gaps to completely fill the gaps; blanket etching the wafer stopping the etch after etching approximately a thickness of the conducting film tc2 to form planarized conducting pillars; photo-etching the conducting pillars over-sizing a photo-mask parallel to the conducting pillars thereby self-aligning the conducting pillars for contact to the conducting lines; and forming a multilevel interconnect to the conducting pillars; whereby the conducting pillars may be utilized to form a multilevel interconnect between the conducting lines and another conducting line.

Claim 8

A method of forming parallel spaced self-aligned conducting pillars in a semiconductor integrated circuit for forming a multilevel interconnect comprising: depositing a conducting layer on a silicon substrate having a gate oxide layer formed thereon; depositing an insulator oxide on the conducting layer; photo-etching to form parallel spaced conducting lines in the conducting layer having spaces of a width C1 therebetween; conformally depositing and anisotropically etching an insulator oxide to form insulating spacers on the sidewalls of the parallel spaced conducting lines while leaving gaps therebetween; conformally depositing a conducting film to a thickness of tc2 over the parallel spaced conducting lines and into the gaps to completely fill the gaps; blanket etching the wafer stopping the etch after etching approximately a thickness of the conducting film tc2 to form planarized conducting pillars; photo-etching the conducting pillars over-sizing a photo-mask parallel to the conducting pillars thereby self-aligning the conducting pillars for contact to the conducting lines; and forming a multilevel interconnect to the conducting pillars; whereby the conducting pillars may be utilized to form a multilevel interconnect between the conducting lines and another conducting line.