US5100816A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming a field effect transistor on the surface of a substrate
Assignee: Texas Instruments Inc
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Filing: 1990-07-20
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Granted: 1992-03-31
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Expires: 2010-07-20
Abstract
Abstract A transistor is disclosed which comprises a gate conductor 34 insulated from a channel region 55 by a gate insulator layer 38. A spacer insulator block 46 is used to accurately space a drain region 52 a predetermined distance from the gate conductor 34. A dopant source body 48 is used to form the drain region 52 such that the formation of the drain region 52 is a self-aligned process. According to the teachings of the present invention, the drain region 52 can be accurately spaced from the gate conductor 34 to reduced field enhanced leakage current during the operation of the transistor.
Inventors
- 👤 Mark S. Rodder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:46
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
151 words
A method for forming a transistor, comprising the steps of: forming a gate conductor; forming a gate insulator adjacent the gate conductor; forming a spacer insulator block having a selected thickness adjacent the gate insulator; forming a channel layer having first, second and third portions, the first portion formed adjacent the gate insulator layer and separated from the gate conductor by the gate insulator, the second portion formed adjacent the spacer insulator block and separated from the gate insulator layer by the spacer insulator block, the third portion formed adjacent the spacer insulator and joining said first and second portions, the channel layer comprising a semiconductor material; forming a drain region in the second portion of the channel layer, the thickness of the spacer insulator block determining the length of the shortest path through the first and third portions of the channel layer between the drain region and the gate insulator.
Claim 2
Independent Claim
151 words
A method for forming a transistor, comprising the steps of: forming a gate conductor; forming a gate insulator adjacent the gate conductor; forming a spacer insulator block having a selected thickness adjacent the gate insulator; forming a channel layer having first, second and third portions, the first portion formed adjacent the gate insulator layer and separated from the gate conductor by the gate insulator, the second portion formed adjacent the spacer insulator block and separated from the gate insulator layer by the spacer insulator block, the third portion formed adjacent the spacer insulator and joining said first and second portions, the channel layer comprising a semiconductor material; forming a drain region in the second portion of the channel layer, the thickness of the spacer insulator block determining the length of the shortest path through the first and third portions of the channel layer between the drain region and the gate insulator.
Claim 3
Dependent Claim
77 words
The method of claim 1 and further comprising the step of forming a dopant source body adjacent the spacer insulator block and the second portion of the channel layer, said step of forming a drain region comprising the step of heating the dopant source body and the second portion of the channel layer such that impurities within the dopant source body diffuse into portions of the second portion of the channel layer adjacent the dopant source body.
Claim 4
Dependent Claim
44 words
The method of claim 1 and further comprising the step of forming a source region in the channel layer spaced apart from the drain region such that the gate conductor is operable to electrically actuate the channel layer between the source and drain regions.
Claim 5
Dependent Claim
27 words
The method of claim 1 wherein said step of forming a gate conductor comprises the step of forming the gate conductor on a surface of a substrate.
Claim 6
Dependent Claim
45 words
The method of claim 1 wherein said step of forming a channel layer comprises the step of forming a channel layer comprising a material selected from the group consisting of polycrystalline semiconductor material, amorphous semiconductor material, partially recrystallized semiconductor material, and wholly recrystallized semiconductor material.
Claim 7
Independent Claim
207 words
A method for forming a transistor on a surface of a substrate, comprising the steps of: forming a gate conductor disposed on the surface; forming a gate insulator layer, a portion of said gate insulator layer adjacent the gate conductor and separated from the surface by the gate conductor; forming a first partial channel layer adjacent the gate insulator layer and separated from the gate conductor by the gate insulator layer; forming a spacer insulator block adjacent the first partial channel layer and separated from the gate insulator layer by the first partial channel layer; forming a dopant source body adjacent the spacer insulator block and separated from the first partial channel layer by the spacer insulator block; forming a second partial channel layer having first, second and third portions, the first portion adjacent the first partial channel layer and separated from the gate insulator layer by the first partial channel layer, the second portion adjacent the spacer insulator block, the third portion adjacent the dopant source body and separated from the spacer insulator block by the dopant source body, the first and second partial channel layers comprising a semiconductor material; and forming a drain region disposed in the third portion of the second partial channel layer.
Claim 8
Independent Claim
207 words
A method for forming a transistor on a surface of a substrate, comprising the steps of: forming a gate conductor disposed on the surface; forming a gate insulator layer, a portion of said gate insulator layer adjacent the gate conductor and separated from the surface by the gate conductor; forming a first partial channel layer adjacent the gate insulator layer and separated from the gate conductor by the gate insulator layer; forming a spacer insulator block adjacent the first partial channel layer and separated from the gate insulator layer by the first partial channel layer; forming a dopant source body adjacent the spacer insulator block and separated from the first partial channel layer by the spacer insulator block; forming a second partial channel layer having first, second and third portions, the first portion adjacent the first partial channel layer and separated from the gate insulator layer by the first partial channel layer, the second portion adjacent the spacer insulator block, the third portion adjacent the dopant source body and separated from the spacer insulator block by the dopant source body, the first and second partial channel layers comprising a semiconductor material; and forming a drain region disposed in the third portion of the second partial channel layer.
Claim 9
Dependent Claim
51 words
The method of claim 6 and further comprising the step of forming a source region in the first portion of the second partial channel layer spaced apart from the drain region, the gate conductor operable to electrically actuate the first and second partial channel layers between the source and drain regions.
Claim 10
Dependent Claim
54 words
The method of claim 6 wherein said step of forming a drain region comprises the step of heating the dopant source body and the third portion of the channel layer such that impurities within the dopant source body diffuse into portions of the third portion of the channel layer adjacent the dopant source body.
References Cited (Backward Citations)
US4882295A
Cited
US4933296A
Cited
US4704783A
Cited
US4988631A
Cited
US4821092A
Cited
US4956680A
Cited
US4968638A
Cited
US4945067A
Cited
US4931353A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-31 | 1995-09-30 | 1996-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-31 | 1999-09-30 | 2000-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-31 | 2003-09-30 | 2004-03-31 | $7700.00 | Window Closed / Lapsed |