Multiple bit error detection and correction system employing a modified Reed-Solomon code incorporating address parity and catastrophic failure detection

Claim 2

In a digital memory system comprising a central processing unit, a memory array and an error detection and correction logic device, a method for generating a plurality of check symbols used for detecting an address error and detecting and correcting a plurality of bit errors in a data word utilizing a Reed-Solomon code, comprising the steps of: a) coupling the memory array and the error detection and correction logic device to the central processing unit; b) coupling the memory array to the error detection and correction logic device; c) transmitting a first data word and address parity information from the central processing unit to the error detection and correction logic device; d) calculating a plurality of check symbols representative of the first data word and the address parity information in the error detection and correction logic device under the control of the Reed-Solomon code using the first data word and the address parity information; and e) storing the first data word and the check symbols in the memory array.

Claim 3

The method of claim 1 wherein the data word comprises N bits and the steps of transmitting the data word, calculating the plurality of check symbols and storing the data word and check symbols are performed on the N bits in parallel operations.

Claim 4

The method of claim 1, further comprising the steps of: a) transmitting a data word from an address in the memory array to the error detection and correction logic device, the data word having a plurality of check symbols representative of the data word and the address parity information; b) calculating a plurality of syndromes in the error detection and correction logic device pursuant to the Reed-Solomon code as a function of the check symbols and the data word wherein the Reed-Solomon code incorporates the address parity information in the plurality of syndromes; c) detecting an address error as a function of the plurality of syndrome; and d) generating an uncorrectable error signal upon detecting the address error.

Claim 5

The method of claim 1, further comprising the steps of: a) transmitting a second data word from an address in the memory array to the error detection and correction logic device, the second data word having a plurality of check symbols representative of the second data word and the address parity information; b) calculating a plurality of syndromes in the error detection and correction logic device pursuant to the Reed-Solomon code as a function of the check symbols and the second data word wherein the Reed-Solomon code incorporates the address parity information in the plurality of syndromes; c) detecting up to a double symbol error in the second data word when the plurality of syndromes are nonzero and generating an uncorrectable error signal upon detecting a double symbol error; and d) correcting a single symbol error in the second data word.

Claim 6

In a digital memory system comprising a central processing unit, a memory array and an error detection logic device, a method for detecting an address error utilizing a Reed-Solomon code, comprising the steps of: a) coupling the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word from an address in the memory array to the error detection logic device, the first data word having a plurality of check symbols representative of the first data word and address parity information; d) calculating a plurality of syndromes in the error detection logic device pursuant to the Reed-Solomon code as a function of the check symbols and the first data word wherein the Reed-Solomon code incorporates the address parity information in the plurality of syndromes; e) detecting an address error as a function of the plurality of syndromes; and f) generating an uncorrectable error signal upon detecting the address error.

Claim 7

In a digital memory system comprising a central processing unit, a memory array and an error detection logic device, a method for detecting an address error utilizing a Reed-Solomon code, comprising the steps of: a) coupling the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word from an address in the memory array to the error detection logic device, the first data word having a plurality of check symbols representative of the first data word and address parity information; d) calculating a plurality of syndromes in the error detection logic device pursuant to the Reed-Solomon code as a function of the check symbols and the first data word wherein the Reed-Solomon code incorporates the address parity information in the plurality of syndromes; e) detecting an address error as a function of the plurality of syndromes; and f) generating an uncorrectable error signal upon detecting the address error.

Claim 8

In a digital memory system comprising a central processing unit, a memory array and an error detection and correction logic device, a method for detecting and correcting a plurality of symbol errors in a data word utilizing a Reed-Solomon code, comprising the steps of: a) coupling the memory array and the error detection and correction logic device to the central processing unit; b) coupling the memory array to the error detection and correction logic device; c) transmitting a first data word from an address in the memory array to the error detection and correction logic device, the first data word having a plurality of check symbols representative of the first data word and address parity information; d) calculating a plurality of syndromes in the error detection and correction logic device pursuant to the Reed-Solomon code as a function of the check symbols and the first data word wherein the Reed-Solomon code incorporates the address parity information in the plurality of syndromes; e) detecting up to a double symbol error in the first data word when the plurality of syndromes are nonzero and generating an uncorrectable error signal upon detecting a double symbol error; and f) correcting a single symbol error in the first data word.

Claim 9

In a digital memory system comprising a central processing unit, a memory array and an error detection and correction logic device, a method for detecting and correcting a plurality of symbol errors in a data word utilizing a Reed-Solomon code, comprising the steps of: a) coupling the memory array and the error detection and correction logic device to the central processing unit; b) coupling the memory array to the error detection and correction logic device; c) transmitting a first data word from an address in the memory array to the error detection and correction logic device, the first data word having a plurality of check symbols representative of the first data word and address parity information; d) calculating a plurality of syndromes in the error detection and correction logic device pursuant to the Reed-Solomon code as a function of the check symbols and the first data word wherein the Reed-Solomon code incorporates the address parity information in the plurality of syndromes; e) detecting up to a double symbol error in the first data word when the plurality of syndromes are nonzero and generating an uncorrectable error signal upon detecting a double symbol error; and f) correcting a single symbol error in the first data word.

Claim 11

In a digital memory system comprising a central processing unit, a memory array and an error detection logic device, a method for generating a plurality of check symbols used for detecting catastrophic error conditions of all ones or all zeros in a data word utilizing a Reed-Solomon code, comprising the steps of: a) coupling each of the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word from the central processing unit to the error detection logic device; d) calculating a plurality of check symbols representative of the first data word in the error detection logic device under the control of the Reed-Solomon code using the first data word; e) complementing at least one bit in each of two of the plurality of the check symbols to provide two partially complemented check symbols; and f) storing the first data word and the plurality of check symbols including the two partially complemented check symbols in the memory array at an address generated by the central processing unit.

Claim 12

In a digital memory system comprising a central processing unit, a memory array and an error detection logic device, a method for generating a plurality of check symbols used for detecting catastrophic error conditions of all ones or all zeros in a data word utilizing a Reed-Solomon code, comprising the steps of: a) coupling each of the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word from the central processing unit to the error detection logic device; d) calculating a plurality of check symbols representative of the first data word in the error detection logic device under the control of the Reed-Solomon code using the first data word; e) complementing at least one bit in each of two of the plurality of the check symbols to provide two partially complemented check symbols; and f) storing the first data word and the plurality of check symbols including the two partially complemented check symbols in the memory array at an address generated by the central processing unit.

Claim 13

The method of claim 8 wherein the first data word comprises N bits and the steps of transmitting the first data word, calculating the plurality of check symbols, complementing the at least one bit in each of two of the plurality of check symbols and storing the first data word and plurality of check symbols are performed on the N bits in parallel operations.

Claim 14

The method of according to claim 8, further comprising the steps of: a) transmitting a second data word from an address in the memory array to the error detection logic device, the second data word comprising a plurality of check symbols wherein two of the plurality of check symbols having at least one bit in each of two of the plurality of check symbols complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the second data word; b) complementing the at least one bit of the two partially complemented check symbols; c) calculating a plurality of syndromes in the error detection logic device pursuant to the Reed-Solomon code as a function of the check symbols and the second data word; d) detecting a data word of all zeros or all ones as a function of the complement of the two partially complemented check symbols; and e) generating a signal indicating an uncorrectable error when the data word is either all zeros or all ones and the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones.

Claim 15

In a digital memory system comprising a central processing unit, a memory array and an error detection logic device, a method for detecting catastrophic error conditions of all ones or all zeros in a data word utilizing a Reed-Solomon code, comprising the steps of: a) coupling each of the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word from an address in the memory array to the error detection logic device, the first data word comprising a plurality of check symbols wherein two of the plurality of check symbols having at least one bit in each of two of the plurality of check symbols complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the first data word; d) complementing the at least one bit of the two partially complemented check symbols; e) calculating a plurality of syndromes in the error detection logic device pursuant to the Reed-Solomon code as a function of the check symbols and the first data word; f) detecting a data word of all zeros or all ones as a function of the complement of the two partially complemented check symbols; and g) generating a signal indicating an uncorrectable error when the data word is either all zeros or all ones and the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones.

Claim 16

In a digital memory system comprising a central processing unit, a memory array and an error detection logic device, a method for detecting catastrophic error conditions of all ones or all zeros in a data word utilizing a Reed-Solomon code, comprising the steps of: a) coupling each of the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word from an address in the memory array to the error detection logic device, the first data word comprising a plurality of check symbols wherein two of the plurality of check symbols having at least one bit in each of two of the plurality of check symbols complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the first data word; d) complementing the at least one bit of the two partially complemented check symbols; e) calculating a plurality of syndromes in the error detection logic device pursuant to the Reed-Solomon code as a function of the check symbols and the first data word; f) detecting a data word of all zeros or all ones as a function of the complement of the two partially complemented check symbols; and g) generating a signal indicating an uncorrectable error when the data word is either all zeros or all ones and the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones.

Claim 18

In a digital memory system comprising a central processing unit, a memory array and an error detection logic device, a method for generating a plurality of check symbols used for detecting catastrophic error conditions of all ones or all zeros in a data word and detecting address errors utilizing a Reed-Solomon code, comprising the steps of: a) coupling each of the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word and address parity information from the central processing unit to the error detection logic device; d) calculating a plurality of check symbols representative of the first data word and the address parity information in the error detection logic device under the control of the Reed-Solomon code using the first data word; e) complementing at least one bit in each of two of the plurality of the check symbols to provide two partially complemented check symbols; and f) storing the first data word and the plurality of check symbols including the two partially complemented check symbols in the memory array at the address generated by the central processing unit.

Claim 19

In a digital memory system comprising a central processing unit, a memory array and an error detection logic device, a method for generating a plurality of check symbols used for detecting catastrophic error conditions of all ones or all zeros in a data word and detecting address errors utilizing a Reed-Solomon code, comprising the steps of: a) coupling each of the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word and address parity information from the central processing unit to the error detection logic device; d) calculating a plurality of check symbols representative of the first data word and the address parity information in the error detection logic device under the control of the Reed-Solomon code using the first data word; e) complementing at least one bit in each of two of the plurality of the check symbols to provide two partially complemented check symbols; and f) storing the first data word and the plurality of check symbols including the two partially complemented check symbols in the memory array at the address generated by the central processing unit.

Claim 20

The method of claim 13 wherein the first data word comprises N bits and the steps of transmitting the first data word, calculating the plurality of check symbols, complementing the at least one bit in each of two of the plurality of check symbols and storing the first data word and plurality of check symbols are performed on the N bits in parallel operations.

Claim 21

The method according to claim 13, further comprising the steps of: a) transmitting a second data word from an address in the memory array to the error detection logic device, the second data word comprising a plurality of check symbols wherein two of the plurality of check symbols having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the second data word and the address parity information; b) complementing the at least one bit of the two partially complemented check symbols; c) calculating a plurality of syndromes in the error detection logic device pursuant to the Reed-Solomon code as a function of the check symbols and the second data word wherein the Reed-Solomon code incorporates the address parity information in the plurality of syndromes; d) detecting a data word of all zeros or all ones as a function of the complement of the two partially complemented check symbols; e) detecting an address error as a function of the plurality of syndromes; and f) generating a signal indicating an uncorrectable error when the data word is either all zeros or all ones and the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones and upon detecting the address error.

Claim 22

In a digital memory system comprising a central processing system, a memory array and an error detection logic device, a method for detecting catastrophic error conditions of all ones or all zeros in a data word and detecting an address error utilizing a Reed-Solomon code, comprising the steps of: a) coupling each of the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word from an address in the memory array to the error detection logic device, the first data word having a plurality of check symbols including two of the plurality of check symbols each having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the first data word and address parity information; d) complementing the at least one bit of the two partially complemented check symbols; e) calculating a plurality of syndromes in the error detection logic device pursuant to the Reed-Solomon code as a function of the plurality of check symbols and the first data word wherein the Reed-Solomon code incorporates address parity information in the plurality of syndromes; f) detecting a data word of all zeros or all ones as a function of the complement of the two partially complemented check symbols; g) detecting an address error as a function of the plurality of syndromes; and h) generating a signal indicating an uncorrectable error when the data word is either all zeros or all ones and the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones and upon detecting the address error.

Claim 23

In a digital memory system comprising a central processing system, a memory array and an error detection logic device, a method for detecting catastrophic error conditions of all ones or all zeros in a data word and detecting an address error utilizing a Reed-Solomon code, comprising the steps of: a) coupling each of the memory array and the error detection logic device to the central processing unit; b) coupling the memory array to the error detection logic device; c) transmitting a first data word from an address in the memory array to the error detection logic device, the first data word having a plurality of check symbols including two of the plurality of check symbols each having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the first data word and address parity information; d) complementing the at least one bit of the two partially complemented check symbols; e) calculating a plurality of syndromes in the error detection logic device pursuant to the Reed-Solomon code as a function of the plurality of check symbols and the first data word wherein the Reed-Solomon code incorporates address parity information in the plurality of syndromes; f) detecting a data word of all zeros or all ones as a function of the complement of the two partially complemented check symbols; g) detecting an address error as a function of the plurality of syndromes; and h) generating a signal indicating an uncorrectable error when the data word is either all zeros or all ones and the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones and upon detecting the address error.

Claim 25

A digital memory system comprising: a memory array; an error detection and correction logic device coupled to the memory array; an input device coupled to the memory array and the error detection and correction logic device, to transmit a data word and address parity information; the error detection and correction logic device to calculate a plurality of check symbols representative of the data word and the address parity information under control of a Reed-Solomon code using the data word and the address parity information.

Claim 26

A digital memory system comprising: a memory array; an error detection and correction logic device coupled to the memory array; an input device coupled to the memory array and the error detection and correction logic device, to transmit a data word and address parity information; the error detection and correction logic device to calculate a plurality of check symbols representative of the data word and the address parity information under control of a Reed-Solomon code using the data word and the address parity information.

Claim 27

The digital memory system of claim 18 wherein the data word comprises N bits, the input device transmits the N bits in a parallel operation and the error detection and correction logic device includes parallel logic to calculate the plurality of check symbols.

Claim 28

The digital memory system of claim 18, further comprising: the input device to transmit a data word from an address in the memory array to the error detection and correction logic device, the data word having a plurality of check symbols representative of the data word and the address parity information; the error detection and correction logic device to calculate a plurality of syndromes under control of a Reed-Solomon code using the data word and the address parity information; and the error detection and correction logic device to detect an address error as a function of the plurality of syndromes and generate an uncorrectable error signal upon detecting the address error.

Claim 29

The digital memory system of claim 18, further comprising: the input device to transmit a data word from an address in the memory array to the error detection and correction logic device, and data word having a plurality of check symbols representative of the data word and the address parity information; the error detection and correction logic device to calculate a plurality of syndromes under control of a Reed-Solomon code using the data word and the address parity information; and the error detection and correction logic device to detect up to a double symbol error in the data word and generate an uncorrectable error signal upon detecting a double symbol error and correct a single symbol error in the data word upon detecting a single symbol error as a function of the plurality of syndromes.

Claim 30

The digital memory system of any one of claims 20 or 21 wherein the data word comprises N bits, the input device includes parallel logic to transmit the N bits and the error detection and correction logic device includes parallel logic to calculate the plurality of syndromes.

Claim 31

A digital memory system comprising: a memory array; an error detection and correction logic device coupled to the memory array; an input device transmitting a data word from an address in the memory array to the error detection and correction logic device, the data word having a plurality of check symbols representative of the data word and address parity information; the error detection and correction logic device to calculate a plurality of syndromes under control of a Reed-Solomon code as a function of the check symbols and the data word using the data word and the address parity information; the error detection and correction logic device to detect an address error as a function of the plurality of syndromes and generate an uncorrectable error signal upon detecting the address error.

Claim 32

A digital memory system comprising: a memory array; an error detection and correction logic device coupled to the memory array; an input device transmitting a data word from an address in the memory array to the error detection and correction logic device, the data word having a plurality of check symbols representative of the data word and address parity information; the error detection and correction logic device to calculate a plurality of syndromes under control of a Reed-Solomon code as a function of the check symbols and the data word using the data word and the address parity information; the error detection and correction logic device to detect an address error as a function of the plurality of syndromes and generate an uncorrectable error signal upon detecting the address error.

Claim 33

A digital memory system comprising: a memory array; an error detection and correction logic device coupled to the memory array; an input device to transmit a data word from an address in the memory array to the error detection and correction logic device, the data word having a plurality of check symbols representative of the data word and address parity information; the error detection and correction logic device to calculate a plurality of syndromes under control of a Reed-Solomon code as a function of the check symbols and the data word using the data word and the address parity information; the error detection and correction logic device to detect up to a double symbol error in the data word and generate an uncorrectable error signal upon detecting a double symbol error and correct a single symbol error in the data word upon detecting a single symbol error as a function of the plurality of syndromes.

Claim 34

A digital memory system comprising: a memory array; an error detection and correction logic device coupled to the memory array; an input device to transmit a data word from an address in the memory array to the error detection and correction logic device, the data word having a plurality of check symbols representative of the data word and address parity information; the error detection and correction logic device to calculate a plurality of syndromes under control of a Reed-Solomon code as a function of the check symbols and the data word using the data word and the address parity information; the error detection and correction logic device to detect up to a double symbol error in the data word and generate an uncorrectable error signal upon detecting a double symbol error and correct a single symbol error in the data word upon detecting a single symbol error as a function of the plurality of syndromes.

Claim 35

The digital memory system of any one of claims 23 or 24 wherein the data word comprises N bits, the input device includes parallel logic to transmit the N bits and the error detection and correction logic device includes parallel logic to calculate the plurality of syndromes.

Claim 36

A digital memory system comprising: a memory array; an error detection logic device coupled tot he memory array; an input device coupled to the memory array and the error detection logic device, the input device to transmit a data word to the error detection logic device; the error detection logic device to calculate a plurality of check symbols representative of the data word under control of a Reed-Solomon code using the data word, to complement at least one bit in each of two of the plurality of check symbols to provide two partially complemented check symbols and to store the data word and the plurality of check symbols including the two partially complemented check symbols in the memory array at an address generated by the input device.

Claim 37

A digital memory system comprising: a memory array; an error detection logic device coupled tot he memory array; an input device coupled to the memory array and the error detection logic device, the input device to transmit a data word to the error detection logic device; the error detection logic device to calculate a plurality of check symbols representative of the data word under control of a Reed-Solomon code using the data word, to complement at least one bit in each of two of the plurality of check symbols to provide two partially complemented check symbols and to store the data word and the plurality of check symbols including the two partially complemented check symbols in the memory array at an address generated by the input device.

Claim 38

The digital memory system of claim 26 wherein the data word comprises N bits, the input device transmits the N bits in a parallel operation, and the error detection logic device includes parallel logic to calculate the plurality of check symbols, complement the at least one bit in the each of two of the plurality of check symbols and store the data word and the plurality of check symbols.

Claim 39

The digital memory system of claim 21, further comprising: the input device to transmit a data word from an address in the memory array to the error detection logic device, the data word having a plurality of check symbols including two of the plurality of check symbols each having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the data word; the error detection logic device to complement the at least one bit of the two partially complemented check symbols and to calculate a plurality of syndromes under control of a Reed-Solomon code using the data word; and the error detection logic device to detect a data word of all zeros or all ones as a function of the two partially complemented check symbols and generate an uncorrectable error signal when the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones.

Claim 40

A digital memory system comprising: a memory array; an error detection logic device coupled to the memory array; an input device coupled to the memory array and the error detection logic device, to transmit a data word from an address in the memory array to the error detection logic device, the data word having a plurality of check symbols including two of the plurality of check symbols each having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the data word; the error detection logic device to complement the at least one bit of the two partially complemented check symbols and to calculate a plurality of syndromes under control of a Reed-Solomon code as a function of the check symbols and the data word using the data word; the error detection logic device to detect a data word of all zeros or all ones as a function of the two partially complemented check symbols and generate an uncorrectable error signal when the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones.

Claim 41

A digital memory system comprising: a memory array; an error detection logic device coupled to the memory array; an input device coupled to the memory array and the error detection logic device, to transmit a data word from an address in the memory array to the error detection logic device, the data word having a plurality of check symbols including two of the plurality of check symbols each having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the data word; the error detection logic device to complement the at least one bit of the two partially complemented check symbols and to calculate a plurality of syndromes under control of a Reed-Solomon code as a function of the check symbols and the data word using the data word; the error detection logic device to detect a data word of all zeros or all ones as a function of the two partially complemented check symbols and generate an uncorrectable error signal when the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones.

Claim 42

The digital memory system of any one of claims 28 or 29 wherein the data word comprises N bits, the input device includes parallel logic to transmit the N bits and the error detection and correction logic device includes parallel logic to complement the at least one bit of the two partially complemented check symbols, to calculate the plurality of syndromes and to detect a data word of all zeros or all ones.

Claim 43

A digital memory system comprising: a memory array; an error detection logic device coupled to the memory array; an input device coupled to the memory array and the error detection logic device, the input device to transmit a data word and address parity information to the error detection logic device; the error detection logic device to calculate a plurality of check symbols representative of the data word and the address parity information under control of a Reed-Solomon code using the data word and the address parity information, to complement at least one bit in each of two of the plurality of check symbols to provide two partially complemented check symbols and to store the data word and the plurality of check symbols including the two partially complemented check symbols in the memory array at an address generated by the input device.

Claim 44

A digital memory system comprising: a memory array; an error detection logic device coupled to the memory array; an input device coupled to the memory array and the error detection logic device, the input device to transmit a data word and address parity information to the error detection logic device; the error detection logic device to calculate a plurality of check symbols representative of the data word and the address parity information under control of a Reed-Solomon code using the data word and the address parity information, to complement at least one bit in each of two of the plurality of check symbols to provide two partially complemented check symbols and to store the data word and the plurality of check symbols including the two partially complemented check symbols in the memory array at an address generated by the input device.

Claim 45

The digital memory system of claim 31 wherein the data word comprises N bits, the input device transmits the N bits in a parallel operation, and the error detection logic device includes parallel logic to calculate the plurality of check symbols, complement the at least one bit in the each of two of the plurality of check symbols and store the data word and the plurality of check symbols.

Claim 46

The digital memory system of claim 31, further comprising: the input device to transmit a data word from an address in the memory array to the error detection logic device, the data word having a plurality of check symbols including two of the plurality of check symbols each having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the data word and the address parity information; the error detection logic device to complement the at least one bit of the two partially complemented check symbols and to calculate a plurality of syndromes under control of a Reed-Solomon code using the data word and the address parity information; and the error detection logic device to detect a data word of all zeros or all ones as a function of the two partially complemented check symbols and to detect an address error and generate and uncorrectable error signal when the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones and upon detecting an address error.

Claim 47

A digital memory system comprising: a memory array; an error detection logic device coupled to the memory array; an input device coupled to the memory array and the error detection logic device, to transmit a data word from an address in the memory array to the error detection logic device, the data word having a plurality of check symbols including two of the plurality of check symbols each having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the data word and address parity information; the error detection logic device to complement the at least one bit of the two partially complemented check symbols and to calculate a plurality of syndromes under control of a Reed-Solomon code as a function of the check symbols and the data word using the data word and the address parity information; the error detection logic device to detect a data word of all zeros or all ones as a function of the two partially complemented check symbols and to detect an address error and generate an uncorrectable error signal when the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones and upon detecting an address error.

Claim 48

A digital memory system comprising: a memory array; an error detection logic device coupled to the memory array; an input device coupled to the memory array and the error detection logic device, to transmit a data word from an address in the memory array to the error detection logic device, the data word having a plurality of check symbols including two of the plurality of check symbols each having at least one bit complemented to provide two partially complemented check symbols, the plurality of check symbols being representative of the data word and address parity information; the error detection logic device to complement the at least one bit of the two partially complemented check symbols and to calculate a plurality of syndromes under control of a Reed-Solomon code as a function of the check symbols and the data word using the data word and the address parity information; the error detection logic device to detect a data word of all zeros or all ones as a function of the two partially complemented check symbols and to detect an address error and generate an uncorrectable error signal when the plurality of syndromes indicate that the check symbols for the data word are not representative of a data word of all zeros or all ones and upon detecting an address error.

Claim 49

The digital memory system of any one of claims 33 or 34 wherein the data word comprises N bits, the input device includes parallel logic to transmit the N bits and the error detection logic device includes parallel logic to complement the at least one bit of the two partially complemented check symbols, to calculate the plurality of syndromes, to detect a data word of all zeros or all ones and to detect an address error.